diff --git a/bpdt-firmware/bpdt-adapter-stm32h5/.cproject b/bpdt-firmware/bpdt-adapter-stm32h5/.cproject index b3b7c90..8ca81b0 100644 --- a/bpdt-firmware/bpdt-adapter-stm32h5/.cproject +++ b/bpdt-firmware/bpdt-adapter-stm32h5/.cproject @@ -1,6 +1,174 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -32,7 +200,7 @@ - @@ -62,7 +230,7 @@ \ No newline at end of file diff --git a/bpdt-firmware/bpdt-adapter-stm32h5/.mxproject b/bpdt-firmware/bpdt-adapter-stm32h5/.mxproject index 098b9ba..b6fbe17 100644 --- a/bpdt-firmware/bpdt-adapter-stm32h5/.mxproject +++ b/bpdt-firmware/bpdt-adapter-stm32h5/.mxproject @@ -1,8 +1,8 @@ [PreviousLibFiles] -LibFiles=Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_cortex.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_cortex.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc_ex.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_bus.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_rcc.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_crs.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_system.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_utils.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash_ex.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio_ex.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_gpio.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma_ex.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_dma.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_dmamux.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr_ex.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_pwr.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_def.h;Drivers\STM32H5xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_exti.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_exti.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_fdcan.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_icache.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_icache.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_usart.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_lpuart.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart_ex.h;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_cortex.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_rcc.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_rcc_ex.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_flash.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_flash_ex.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_gpio.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_dma.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_dma_ex.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_pwr.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_pwr_ex.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_exti.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_fdcan.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_icache.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_uart.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_uart_ex.c;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_cortex.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_cortex.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc_ex.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_bus.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_rcc.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_crs.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_system.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_utils.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash_ex.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio_ex.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_gpio.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma_ex.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_dma.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_dmamux.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr_ex.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_pwr.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_def.h;Drivers\STM32H5xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_exti.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_exti.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_fdcan.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_icache.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_icache.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_usart.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_lpuart.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart_ex.h;Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h533xx.h;Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h5xx.h;Drivers\CMSIS\Device\ST\STM32H5xx\Include\system_stm32h5xx.h;Drivers\CMSIS\Device\ST\STM32H5xx\Include\system_stm32h5xx.h;Drivers\CMSIS\Device\ST\STM32H5xx\Source\Templates\system_stm32h5xx.c;Drivers\CMSIS\Include\cachel1_armv7.h;Drivers\CMSIS\Include\cmsis_armcc.h;Drivers\CMSIS\Include\cmsis_armclang.h;Drivers\CMSIS\Include\cmsis_armclang_ltm.h;Drivers\CMSIS\Include\cmsis_compiler.h;Drivers\CMSIS\Include\cmsis_gcc.h;Drivers\CMSIS\Include\cmsis_iccarm.h;Drivers\CMSIS\Include\cmsis_version.h;Drivers\CMSIS\Include\core_armv81mml.h;Drivers\CMSIS\Include\core_armv8mbl.h;Drivers\CMSIS\Include\core_armv8mml.h;Drivers\CMSIS\Include\core_cm0.h;Drivers\CMSIS\Include\core_cm0plus.h;Drivers\CMSIS\Include\core_cm1.h;Drivers\CMSIS\Include\core_cm23.h;Drivers\CMSIS\Include\core_cm3.h;Drivers\CMSIS\Include\core_cm33.h;Drivers\CMSIS\Include\core_cm35p.h;Drivers\CMSIS\Include\core_cm4.h;Drivers\CMSIS\Include\core_cm55.h;Drivers\CMSIS\Include\core_cm7.h;Drivers\CMSIS\Include\core_cm85.h;Drivers\CMSIS\Include\core_sc000.h;Drivers\CMSIS\Include\core_sc300.h;Drivers\CMSIS\Include\core_starmc1.h;Drivers\CMSIS\Include\mpu_armv7.h;Drivers\CMSIS\Include\mpu_armv8.h;Drivers\CMSIS\Include\pac_armv81.h;Drivers\CMSIS\Include\pmu_armv8.h;Drivers\CMSIS\Include\tz_context.h; +LibFiles=Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_cortex.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_cortex.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc_ex.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_bus.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_rcc.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_crs.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_system.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_utils.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash_ex.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio_ex.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_gpio.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma_ex.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_dma.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_dmamux.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr_ex.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_pwr.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_def.h;Drivers\STM32H5xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_exti.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_exti.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_fdcan.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_usart.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_lpuart.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart_ex.h;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_cortex.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_rcc.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_rcc_ex.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_flash.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_flash_ex.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_gpio.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_dma.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_dma_ex.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_pwr.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_pwr_ex.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_exti.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_fdcan.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_uart.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_uart_ex.c;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_cortex.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_cortex.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc_ex.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_bus.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_rcc.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_crs.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_system.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_utils.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash_ex.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio_ex.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_gpio.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma_ex.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_dma.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_dmamux.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr_ex.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_pwr.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_def.h;Drivers\STM32H5xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_exti.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_exti.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_fdcan.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_usart.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_lpuart.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart_ex.h;Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h533xx.h;Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h5xx.h;Drivers\CMSIS\Device\ST\STM32H5xx\Include\system_stm32h5xx.h;Drivers\CMSIS\Device\ST\STM32H5xx\Include\system_stm32h5xx.h;Drivers\CMSIS\Device\ST\STM32H5xx\Source\Templates\system_stm32h5xx.c;Drivers\CMSIS\Include\cachel1_armv7.h;Drivers\CMSIS\Include\cmsis_armcc.h;Drivers\CMSIS\Include\cmsis_armclang.h;Drivers\CMSIS\Include\cmsis_armclang_ltm.h;Drivers\CMSIS\Include\cmsis_compiler.h;Drivers\CMSIS\Include\cmsis_gcc.h;Drivers\CMSIS\Include\cmsis_iccarm.h;Drivers\CMSIS\Include\cmsis_version.h;Drivers\CMSIS\Include\core_armv81mml.h;Drivers\CMSIS\Include\core_armv8mbl.h;Drivers\CMSIS\Include\core_armv8mml.h;Drivers\CMSIS\Include\core_cm0.h;Drivers\CMSIS\Include\core_cm0plus.h;Drivers\CMSIS\Include\core_cm1.h;Drivers\CMSIS\Include\core_cm23.h;Drivers\CMSIS\Include\core_cm3.h;Drivers\CMSIS\Include\core_cm33.h;Drivers\CMSIS\Include\core_cm35p.h;Drivers\CMSIS\Include\core_cm4.h;Drivers\CMSIS\Include\core_cm55.h;Drivers\CMSIS\Include\core_cm7.h;Drivers\CMSIS\Include\core_cm85.h;Drivers\CMSIS\Include\core_sc000.h;Drivers\CMSIS\Include\core_sc300.h;Drivers\CMSIS\Include\core_starmc1.h;Drivers\CMSIS\Include\mpu_armv7.h;Drivers\CMSIS\Include\mpu_armv8.h;Drivers\CMSIS\Include\pac_armv81.h;Drivers\CMSIS\Include\pmu_armv8.h;Drivers\CMSIS\Include\tz_context.h; [PreviousUsedCubeIDEFiles] -SourceFiles=Core\Src\main.c;Core\Src\stm32h5xx_it.c;Core\Src\stm32h5xx_hal_msp.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_cortex.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_rcc.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_rcc_ex.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_flash.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_flash_ex.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_gpio.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_dma.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_dma_ex.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_pwr.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_pwr_ex.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_exti.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_fdcan.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_icache.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_uart.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_uart_ex.c;Drivers\CMSIS\Device\ST\STM32H5xx\Source\Templates\system_stm32h5xx.c;Core\Src\system_stm32h5xx.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_cortex.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_rcc.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_rcc_ex.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_flash.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_flash_ex.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_gpio.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_dma.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_dma_ex.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_pwr.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_pwr_ex.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_exti.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_fdcan.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_icache.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_uart.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_uart_ex.c;Drivers\CMSIS\Device\ST\STM32H5xx\Source\Templates\system_stm32h5xx.c;Core\Src\system_stm32h5xx.c;;; +SourceFiles=Core\Src\main.c;Core\Src\stm32h5xx_it.c;Core\Src\stm32h5xx_hal_msp.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_cortex.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_rcc.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_rcc_ex.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_flash.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_flash_ex.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_gpio.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_dma.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_dma_ex.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_pwr.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_pwr_ex.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_exti.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_fdcan.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_uart.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_uart_ex.c;Drivers\CMSIS\Device\ST\STM32H5xx\Source\Templates\system_stm32h5xx.c;Core\Src\system_stm32h5xx.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_cortex.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_rcc.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_rcc_ex.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_flash.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_flash_ex.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_gpio.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_dma.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_dma_ex.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_pwr.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_pwr_ex.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_exti.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_fdcan.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_uart.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_uart_ex.c;Drivers\CMSIS\Device\ST\STM32H5xx\Source\Templates\system_stm32h5xx.c;Core\Src\system_stm32h5xx.c;;; HeaderPath=Drivers\STM32H5xx_HAL_Driver\Inc;Drivers\STM32H5xx_HAL_Driver\Inc\Legacy;Drivers\CMSIS\Device\ST\STM32H5xx\Include;Drivers\CMSIS\Include;Core\Inc; CDefines=USE_HAL_DRIVER;STM32H533xx;USE_HAL_DRIVER;USE_HAL_DRIVER; diff --git a/bpdt-firmware/bpdt-adapter-stm32h5/.settings/com.st.stm32cube.ide.mcu.sfrview.prefs b/bpdt-firmware/bpdt-adapter-stm32h5/.settings/com.st.stm32cube.ide.mcu.sfrview.prefs new file mode 100644 index 0000000..98a69fc --- /dev/null +++ b/bpdt-firmware/bpdt-adapter-stm32h5/.settings/com.st.stm32cube.ide.mcu.sfrview.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +sfrviewstate={"fFavorites"\:{"fLists"\:{}},"fProperties"\:{"fNodeProperties"\:{}}} diff --git a/bpdt-firmware/bpdt-adapter-stm32h5/.settings/org.eclipse.cdt.core.prefs b/bpdt-firmware/bpdt-adapter-stm32h5/.settings/org.eclipse.cdt.core.prefs deleted file mode 100644 index c8ec5df..0000000 --- a/bpdt-firmware/bpdt-adapter-stm32h5/.settings/org.eclipse.cdt.core.prefs +++ /dev/null @@ -1,6 +0,0 @@ -doxygen/doxygen_new_line_after_brief=true -doxygen/doxygen_use_brief_tag=false -doxygen/doxygen_use_javadoc_tags=true -doxygen/doxygen_use_pre_tag=false -doxygen/doxygen_use_structural_commands=false -eclipse.preferences.version=1 diff --git a/bpdt-firmware/bpdt-adapter-stm32h5/.settings/stm32cubeide.project.prefs b/bpdt-firmware/bpdt-adapter-stm32h5/.settings/stm32cubeide.project.prefs index 3884970..ba84fc3 100644 --- a/bpdt-firmware/bpdt-adapter-stm32h5/.settings/stm32cubeide.project.prefs +++ b/bpdt-firmware/bpdt-adapter-stm32h5/.settings/stm32cubeide.project.prefs @@ -1,4 +1,4 @@ -2F62501ED4689FB349E356AB974DBE57=5FF411E02804450150C03BCD0341ADB7 -8DF89ED150041C4CBC7CB9A9CAA90856=5FF411E02804450150C03BCD0341ADB7 +2F62501ED4689FB349E356AB974DBE57=2C05865D3F922AF2D6DEA2C91D6CFD10 +8DF89ED150041C4CBC7CB9A9CAA90856=2C05865D3F922AF2D6DEA2C91D6CFD10 DC22A860405A8BF2F2C095E5B6529F12=D379B132D77101410ADD6FD5B0C1605E eclipse.preferences.version=1 diff --git a/bpdt-firmware/bpdt-adapter-stm32h5/Core/BT_HC06_Libs/hc_06.c b/bpdt-firmware/bpdt-adapter-stm32h5/Core/BT_HC06_Libs/hc_06.c index 71f4f3c..5d92409 100644 --- a/bpdt-firmware/bpdt-adapter-stm32h5/Core/BT_HC06_Libs/hc_06.c +++ b/bpdt-firmware/bpdt-adapter-stm32h5/Core/BT_HC06_Libs/hc_06.c @@ -5,7 +5,7 @@ #include "IKW1281Connection.h" #include "kline.h" -extern UART_HandleTypeDef huart2; +extern UART_HandleTypeDef huart3; /* ========================= TX delay / non-blocking queue @@ -67,7 +67,7 @@ static void HC06_TxKick(void) // wait until due timestamp if ((int32_t)(HAL_GetTick() - it->due_ms) < 0) return; - if (HAL_UART_Transmit_IT(&huart2, it->buf, it->len) == HAL_OK) { + if (HAL_UART_Transmit_IT(&huart3, it->buf, it->len) == HAL_OK) { s_tx_busy = 1u; } } @@ -76,7 +76,7 @@ static void HC06_TxKick(void) void HC06_UART_TxCpltCallback(UART_HandleTypeDef *huart) { if (!huart) return; - if (huart->Instance != huart2.Instance) return; + if (huart->Instance != huart3.Instance) return; if (!s_tx_busy) return; // pop the item that just finished @@ -111,7 +111,7 @@ static void BT_ReadAudiPin(void); USER SETTINGS (edit) ========================= */ #define HC06_DO_AT_SETUP_AT_BOOT 1 -#define HC06_NAME "HC - dFi Tool v1" +#define HC06_NAME "HC - BPDT - Adapter" // Many HC-06 firmwares do NOT support PIN change; leave disabled unless proven. #define HC06_TRY_SET_PIN 0 @@ -227,7 +227,7 @@ float HC06_DfiS16ToFloat(int16_t s) HAL_StatusTypeDef HC06_SendAscii(const char *s) { if (!s) return HAL_ERROR; - return HAL_UART_Transmit(&huart2, (uint8_t*)s, (uint16_t)strlen(s), 200); + return HAL_UART_Transmit(&huart3, (uint8_t*)s, (uint16_t)strlen(s), 200); } HAL_StatusTypeDef HC06_SendAsciiLn(const char *s) @@ -377,7 +377,7 @@ static HAL_StatusTypeDef HC06_SendDataReply(uint8_t status, const uint8_t *paylo ========================= */ void HC06_UART_RxByteCallback(UART_HandleTypeDef *huart) { - if (huart->Instance != huart2.Instance) return; + if (huart->Instance != huart3.Instance) return; uint8_t x = rx_byte; @@ -397,7 +397,7 @@ void HC06_UART_RxByteCallback(UART_HandleTypeDef *huart) } // continue RX - HAL_UART_Receive_IT(&huart2, &rx_byte, 1); + HAL_UART_Receive_IT(&huart3, &rx_byte, 1); return; } @@ -463,7 +463,7 @@ void HC06_UART_RxByteCallback(UART_HandleTypeDef *huart) break; } - HAL_UART_Receive_IT(&huart2, &rx_byte, 1); + HAL_UART_Receive_IT(&huart3, &rx_byte, 1); } /* ========================= @@ -612,22 +612,22 @@ void HC06_Process(void) static void HC06_ForceRearmRx(void) { // Stop anything currently running on UART2 - HAL_UART_AbortReceive_IT(&huart2); - HAL_UART_AbortReceive(&huart2); - HAL_UART_AbortTransmit(&huart2); + HAL_UART_AbortReceive_IT(&huart3); + HAL_UART_AbortReceive(&huart3); + HAL_UART_AbortTransmit(&huart3); // Reset queued TX as well (avoid sending stale frames after re-arm) HC06_TxReset(); // Clear UART error flags properly - __HAL_UART_CLEAR_OREFLAG(&huart2); - __HAL_UART_CLEAR_NEFLAG(&huart2); - __HAL_UART_CLEAR_FEFLAG(&huart2); - __HAL_UART_CLEAR_PEFLAG(&huart2); + __HAL_UART_CLEAR_OREFLAG(&huart3); + __HAL_UART_CLEAR_NEFLAG(&huart3); + __HAL_UART_CLEAR_FEFLAG(&huart3); + __HAL_UART_CLEAR_PEFLAG(&huart3); // Ensure peripheral interrupt enable bits are set - __HAL_UART_ENABLE_IT(&huart2, UART_IT_RXNE); - __HAL_UART_ENABLE_IT(&huart2, UART_IT_ERR); + __HAL_UART_ENABLE_IT(&huart3, UART_IT_RXNE); + __HAL_UART_ENABLE_IT(&huart3, UART_IT_ERR); // Also clear any pending interrupt in NVIC (rare but helps) NVIC_ClearPendingIRQ(USART2_IRQn); @@ -639,7 +639,7 @@ static void HC06_ForceRearmRx(void) AT_Clear(); // Rearm 1-byte RX no matter what mode - HAL_StatusTypeDef rst = HAL_UART_Receive_IT(&huart2, &rx_byte, 1); + HAL_StatusTypeDef rst = HAL_UART_Receive_IT(&huart3, &rx_byte, 1); (void)rst; crc = 0; } diff --git a/bpdt-firmware/bpdt-adapter-stm32h5/Core/Inc/main.h b/bpdt-firmware/bpdt-adapter-stm32h5/Core/Inc/main.h index cb9ec44..c57b305 100644 --- a/bpdt-firmware/bpdt-adapter-stm32h5/Core/Inc/main.h +++ b/bpdt-firmware/bpdt-adapter-stm32h5/Core/Inc/main.h @@ -31,13 +31,13 @@ extern "C" { /* Private includes ----------------------------------------------------------*/ /* USER CODE BEGIN Includes */ - +extern UART_HandleTypeDef huart1; +extern UART_HandleTypeDef huart2; /* USER CODE END Includes */ /* Exported types ------------------------------------------------------------*/ /* USER CODE BEGIN ET */ -extern UART_HandleTypeDef huart1; -extern UART_HandleTypeDef huart2; + /* USER CODE END ET */ /* Exported constants --------------------------------------------------------*/ @@ -58,14 +58,6 @@ void Error_Handler(void); /* USER CODE END EFP */ /* Private defines -----------------------------------------------------------*/ -#define SWDIO_Pin GPIO_PIN_13 -#define SWDIO_GPIO_Port GPIOA -#define SWCLK_Pin GPIO_PIN_14 -#define SWCLK_GPIO_Port GPIOA -#define JTDI_Pin GPIO_PIN_15 -#define JTDI_GPIO_Port GPIOA -#define SWO_Pin GPIO_PIN_3 -#define SWO_GPIO_Port GPIOB /* USER CODE BEGIN Private defines */ diff --git a/bpdt-firmware/bpdt-adapter-stm32h5/Core/Inc/stm32h5xx_hal_conf.h b/bpdt-firmware/bpdt-adapter-stm32h5/Core/Inc/stm32h5xx_hal_conf.h index d7d0f80..00b085f 100644 --- a/bpdt-firmware/bpdt-adapter-stm32h5/Core/Inc/stm32h5xx_hal_conf.h +++ b/bpdt-firmware/bpdt-adapter-stm32h5/Core/Inc/stm32h5xx_hal_conf.h @@ -75,7 +75,7 @@ /*#define HAL_USART_MODULE_ENABLED */ /*#define HAL_WWDG_MODULE_ENABLED */ /*#define HAL_PSSI_MODULE_ENABLED */ -#define HAL_ICACHE_MODULE_ENABLED +/*#define HAL_ICACHE_MODULE_ENABLED */ /*#define HAL_PCD_MODULE_ENABLED */ /*#define HAL_HCD_MODULE_ENABLED */ /*#define HAL_SMARTCARD_MODULE_ENABLED */ @@ -97,7 +97,7 @@ * (when HSE is used as system clock source, directly or through the PLL). */ #if !defined (HSE_VALUE) - #define HSE_VALUE 25000000U /*!< Value of the External oscillator in Hz */ + #define HSE_VALUE 24000000U /*!< Value of the External oscillator in Hz */ #endif /* HSE_VALUE */ #if !defined (HSE_STARTUP_TIMEOUT) diff --git a/bpdt-firmware/bpdt-adapter-stm32h5/Core/Inc/stm32h5xx_it.h b/bpdt-firmware/bpdt-adapter-stm32h5/Core/Inc/stm32h5xx_it.h index ae5b3a5..80713de 100644 --- a/bpdt-firmware/bpdt-adapter-stm32h5/Core/Inc/stm32h5xx_it.h +++ b/bpdt-firmware/bpdt-adapter-stm32h5/Core/Inc/stm32h5xx_it.h @@ -55,6 +55,8 @@ void SVC_Handler(void); void DebugMon_Handler(void); void PendSV_Handler(void); void SysTick_Handler(void); +void USART1_IRQHandler(void); +void USART3_IRQHandler(void); /* USER CODE BEGIN EFP */ /* USER CODE END EFP */ diff --git a/bpdt-firmware/bpdt-adapter-stm32h5/Core/Kline_Master_Libs/IKW1281Connection.c b/bpdt-firmware/bpdt-adapter-stm32h5/Core/Kline_Master_Libs/IKW1281Connection.c index 6ec905d..5b45a26 100644 --- a/bpdt-firmware/bpdt-adapter-stm32h5/Core/Kline_Master_Libs/IKW1281Connection.c +++ b/bpdt-firmware/bpdt-adapter-stm32h5/Core/Kline_Master_Libs/IKW1281Connection.c @@ -25,35 +25,35 @@ uint8_t timeoutdata[] = "TimeoutNigga\r\n"; //uint8_t RxData[1]; uint8_t TxData[KLINE_BUFFER_SIZE]; uint8_t KlineData[KLINE_BUFFER_SIZE]; -volatile uint8_t rx_done_flag = 0; +extern volatile uint8_t rx_done_flag; uint8_t connectionAlive = 0; -uint8_t ReadByte(){ - if (!connectionAlive){ return 0;} - rx_done_flag = 0; - uint32_t timeout = HAL_GetTick() + 1000; // 1-second timeout - while (!rx_done_flag) - { - if (HAL_GetTick() > timeout) { - // Timeout occurred +uint8_t ReadByte(void) +{ + if (!connectionAlive) return 0; - //HAL_UART_Transmit(&huart2, (uint8_t*)timeoutdata, strlen(timeoutdata), 1000); - //CDC_Transmit_FS((uint8_t*)timeoutdata, strlen(timeoutdata)); - connectionAlive = 0; - return 0xFF; // Or some special error code - } + rx_done_flag = 0; - // Optional: add a timeout check here - // This loop blocks until RX is done - } - /*for (int k = 0; k < KLINE_BUFFER_SIZE ; k++){ - KlineData[k]=KlineData[k+1]; - } - KlineData[KLINE_BUFFER_SIZE] = 0; - return KlineData[0];*/ - return RxData[0]; + // Re-arm UART RX interrupt for next byte + HAL_UART_Receive_IT(&huart1, (uint8_t*)&k_rx_byte, 1); + + uint32_t timeout = HAL_GetTick() + 1000; + while (!rx_done_flag) + { + if ((int32_t)(HAL_GetTick() - timeout) >= 0) + { + HAL_UART_AbortReceive(&huart1); // cancel the pending IT + connectionAlive = 0; + return 0xFF; + } + } + + // Safely capture the byte (atomic copy) + uint8_t b = k_rx_byte; + return b; } + uint8_t ReadAndAckByte(void){ uint8_t b = ReadByte(); WriteComplement(b); @@ -81,10 +81,7 @@ void WriteByteRaw(uint8_t b){ #define MAX_PACKETS 16 // adjust to your needs static ParsedPacket packets_buffer[MAX_PACKETS]; -#define MAX_PACKETS 16 -// static buffer, persistent between calls -static ParsedPacket packets_buffer[MAX_PACKETS]; ParsedPacket* ReceivePackets(int *out_count) { @@ -99,11 +96,12 @@ ParsedPacket* ReceivePackets(int *out_count) ParsedPacket packet = ReceivePacket(); packets_buffer[count++] = packet; - if (packet.isAckNak) { + if (packet.isAckNak || !connectionAlive) { break; } SendAckPacket(); + } if (out_count) { @@ -149,6 +147,8 @@ uint8_t _packetCounterInitialized = 0; ParsedPacket ReceivePacket() { ParsedPacket packet = {0}; + if (!connectionAlive) return packet; // add this + uint8_t index = 0; uint8_t packetLength = ReadAndAckByte(); @@ -261,6 +261,8 @@ void WriteByteAndReadAck(uint8_t b) WriteByteRaw(b); uint8_t ack = ReadByte(); + HAL_UART_AbortReceive(&huart1); + uint8_t expectedAck = (uint8_t)~b; if (ack != expectedAck) { diff --git a/bpdt-firmware/bpdt-adapter-stm32h5/Core/Kline_Master_Libs/IKW1281Connection.h b/bpdt-firmware/bpdt-adapter-stm32h5/Core/Kline_Master_Libs/IKW1281Connection.h index 9f49127..5e69461 100644 --- a/bpdt-firmware/bpdt-adapter-stm32h5/Core/Kline_Master_Libs/IKW1281Connection.h +++ b/bpdt-firmware/bpdt-adapter-stm32h5/Core/Kline_Master_Libs/IKW1281Connection.h @@ -11,7 +11,7 @@ #include #include "stdint.h" -extern uint8_t RxData[]; +extern volatile uint8_t k_rx_byte; extern volatile uint8_t rx_done_flag; extern uint8_t connectionAlive; @@ -23,7 +23,7 @@ extern uint8_t connectionAlive; //typedef uint8_t PacketCommand; -#define MAX_PACKET_SIZE 512 // if too big it will crash 128Instance == huart2.Instance) + if (huart->Instance == huart3.Instance) { HC06_UART_RxByteCallback(huart); - }else{ - rx_done_flag = 1; - HAL_UART_Receive_IT(&huart1, RxData, 1); + } + if (huart->Instance == USART1) + { + rx_done_flag = 1; + // Do NOT re-arm here. ReadByte() does it. } } @@ -99,6 +92,8 @@ uint8_t sent_init_message = 0; uint8_t psg_connected = 0; void OnEnterReceived(void) { + //char msg[] = "Enter pressed!\r\n"; + //CDC_Transmit_FS((uint8_t*)msg, strlen(msg)); BitBang = 1; } @@ -107,24 +102,12 @@ uint32_t alive_due_ms =0; void TryConnection(void){ BitBang = 0; - char data[32]; - - /*sprintf(data, "Starting communication with PSGx...\r\n"); - CDC_Transmit_FS((uint8_t*)data, strlen(data)); - sprintf(data, "\r\n"); - CDC_Transmit_FS((uint8_t*)data, strlen(data)); - */ int protocolVersion = WakeUp(ECU_INIT_ADDRESS, 0); - //WriteByteRaw(0x69); - //memset(data, 0, sizeof data); - /*sprintf(data, "Protocol Version : %d\t\r\n", protocolVersion); - CDC_Transmit_FS((uint8_t*)data, strlen(data));*/ - //HAL_UART_Transmit(&huart2, data, 12, 1000); + if (!protocolVersion || !connectionAlive) return; // add connectionAlive check ecuinfo = ReadEcuInfo(); - //PrintEcuInfo(&ecuinfo); if(!KeepAlive()){ KLINE_THROW_NONALIVE_EXCEPTION(4); return; @@ -174,18 +157,14 @@ int main(void) /* Initialize all configured peripherals */ MX_GPIO_Init(); - MX_ICACHE_Init(); MX_FDCAN1_Init(); - MX_FDCAN2_Init(); - MX_UART4_Init(); - MX_UART5_Init(); MX_USART1_UART_Init(); - MX_USART2_UART_Init(); MX_USART3_UART_Init(); - MX_USART6_UART_Init(); /* USER CODE BEGIN 2 */ - HAL_UART_Receive_IT(&huart1, RxData, 1); - //HAL_Delay(25); // Wait before starting UART (standard KWP wait time) + //HAL_UART_Receive_IT(&huart1, &k_rx_byte, 1); + HAL_Delay(25); // Wait before starting UART (standard KWP wait time) + //int protocolVersion = WakeUp(ECU_INIT_ADDRESS, 0); + HC06_Init(); HC06_AT_BootSetup(); // sets NAME, then switches to BIN mode /* USER CODE END 2 */ @@ -198,35 +177,25 @@ int main(void) /* USER CODE BEGIN 3 */ - HC06_Process(); - - /*if(pc_connected && !sent_init_message){ - sprintf(data, "Press any key to read data...\r\n"); - CDC_Transmit_FS((uint8_t*)data, strlen(data)); - sent_init_message = 1; - }*/ - //HAL_UART_Transmit_DMA(&huart1, data, 5); - //CDC_Transmit_FS((uint8_t*)data, strlen(data)); - - - if(BitBang){ - //HAL_GPIO_WritePin(KLINE_GPIO_PORT, GPIO_PIN_8, GPIO_PIN_RESET); - TryConnection(); - //AQUI HARIA FALTA IMPLEMENTAR UN TIMER QUE CADA x ms haga un keep alive - //EndCommunication(); - } - if(psg_connected){ - if ((int32_t)(HAL_GetTick() - alive_due_ms) < 0){ - if(!KeepAlive()){ - KLINE_THROW_NONALIVE_EXCEPTION(4); - psg_connected = 0; - //return; - } - BT_SendCommStatus(); - alive_due_ms = HAL_GetTick() + 500; + HC06_Process(); + if(BitBang){ + //HAL_GPIO_WritePin(KLINE_GPIO_PORT, GPIO_PIN_8, GPIO_PIN_RESET); + TryConnection(); + //AQUI HARIA FALTA IMPLEMENTAR UN TIMER QUE CADA x ms haga un keep alive + //EndCommunication(); + } + if(psg_connected){ + if ((int32_t)(HAL_GetTick() - alive_due_ms) >= 0){ + if(!KeepAlive()){ + KLINE_THROW_NONALIVE_EXCEPTION(4); + psg_connected = 0; + //return; } - + BT_SendCommStatus(); + alive_due_ms = HAL_GetTick() + 500; } + + } } /* USER CODE END 3 */ } @@ -242,19 +211,25 @@ void SystemClock_Config(void) /** Configure the main internal regulator output voltage */ - __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3); + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2); while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; RCC_OscInitStruct.HSEState = RCC_HSE_ON; - RCC_OscInitStruct.HSIState = RCC_HSI_ON; - RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV2; - RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLL1_SOURCE_HSE; + RCC_OscInitStruct.PLL.PLLM = 2; + RCC_OscInitStruct.PLL.PLLN = 20; + RCC_OscInitStruct.PLL.PLLP = 2; + RCC_OscInitStruct.PLL.PLLQ = 2; + RCC_OscInitStruct.PLL.PLLR = 2; + RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1_VCIRANGE_3; + RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1_VCORANGE_WIDE; + RCC_OscInitStruct.PLL.PLLFRACN = 0; if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { Error_Handler(); @@ -265,20 +240,20 @@ void SystemClock_Config(void) RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2 |RCC_CLOCKTYPE_PCLK3; - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; RCC_ClkInitStruct.APB3CLKDivider = RCC_HCLK_DIV1; - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) { Error_Handler(); } /** Configure the programming delay */ - __HAL_FLASH_SET_PROGRAM_DELAY(FLASH_PROGRAMMING_DELAY_0); + __HAL_FLASH_SET_PROGRAM_DELAY(FLASH_PROGRAMMING_DELAY_1); } /** @@ -324,177 +299,6 @@ static void MX_FDCAN1_Init(void) } -/** - * @brief FDCAN2 Initialization Function - * @param None - * @retval None - */ -static void MX_FDCAN2_Init(void) -{ - - /* USER CODE BEGIN FDCAN2_Init 0 */ - - /* USER CODE END FDCAN2_Init 0 */ - - /* USER CODE BEGIN FDCAN2_Init 1 */ - - /* USER CODE END FDCAN2_Init 1 */ - hfdcan2.Instance = FDCAN2; - hfdcan2.Init.ClockDivider = FDCAN_CLOCK_DIV1; - hfdcan2.Init.FrameFormat = FDCAN_FRAME_CLASSIC; - hfdcan2.Init.Mode = FDCAN_MODE_NORMAL; - hfdcan2.Init.AutoRetransmission = DISABLE; - hfdcan2.Init.TransmitPause = DISABLE; - hfdcan2.Init.ProtocolException = DISABLE; - hfdcan2.Init.NominalPrescaler = 16; - hfdcan2.Init.NominalSyncJumpWidth = 1; - hfdcan2.Init.NominalTimeSeg1 = 1; - hfdcan2.Init.NominalTimeSeg2 = 1; - hfdcan2.Init.DataPrescaler = 1; - hfdcan2.Init.DataSyncJumpWidth = 1; - hfdcan2.Init.DataTimeSeg1 = 1; - hfdcan2.Init.DataTimeSeg2 = 1; - hfdcan2.Init.StdFiltersNbr = 0; - hfdcan2.Init.ExtFiltersNbr = 0; - hfdcan2.Init.TxFifoQueueMode = FDCAN_TX_FIFO_OPERATION; - if (HAL_FDCAN_Init(&hfdcan2) != HAL_OK) - { - Error_Handler(); - } - /* USER CODE BEGIN FDCAN2_Init 2 */ - - /* USER CODE END FDCAN2_Init 2 */ - -} - -/** - * @brief ICACHE Initialization Function - * @param None - * @retval None - */ -static void MX_ICACHE_Init(void) -{ - - /* USER CODE BEGIN ICACHE_Init 0 */ - - /* USER CODE END ICACHE_Init 0 */ - - /* USER CODE BEGIN ICACHE_Init 1 */ - - /* USER CODE END ICACHE_Init 1 */ - - /** Enable instruction cache in 1-way (direct mapped cache) - */ - if (HAL_ICACHE_ConfigAssociativityMode(ICACHE_1WAY) != HAL_OK) - { - Error_Handler(); - } - if (HAL_ICACHE_Enable() != HAL_OK) - { - Error_Handler(); - } - /* USER CODE BEGIN ICACHE_Init 2 */ - - /* USER CODE END ICACHE_Init 2 */ - -} - -/** - * @brief UART4 Initialization Function - * @param None - * @retval None - */ -static void MX_UART4_Init(void) -{ - - /* USER CODE BEGIN UART4_Init 0 */ - - /* USER CODE END UART4_Init 0 */ - - /* USER CODE BEGIN UART4_Init 1 */ - - /* USER CODE END UART4_Init 1 */ - huart4.Instance = UART4; - huart4.Init.BaudRate = 115200; - huart4.Init.WordLength = UART_WORDLENGTH_8B; - huart4.Init.StopBits = UART_STOPBITS_1; - huart4.Init.Parity = UART_PARITY_NONE; - huart4.Init.Mode = UART_MODE_TX_RX; - huart4.Init.HwFlowCtl = UART_HWCONTROL_NONE; - huart4.Init.OverSampling = UART_OVERSAMPLING_16; - huart4.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; - huart4.Init.ClockPrescaler = UART_PRESCALER_DIV1; - huart4.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; - if (HAL_UART_Init(&huart4) != HAL_OK) - { - Error_Handler(); - } - if (HAL_UARTEx_SetTxFifoThreshold(&huart4, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) - { - Error_Handler(); - } - if (HAL_UARTEx_SetRxFifoThreshold(&huart4, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) - { - Error_Handler(); - } - if (HAL_UARTEx_DisableFifoMode(&huart4) != HAL_OK) - { - Error_Handler(); - } - /* USER CODE BEGIN UART4_Init 2 */ - - /* USER CODE END UART4_Init 2 */ - -} - -/** - * @brief UART5 Initialization Function - * @param None - * @retval None - */ -static void MX_UART5_Init(void) -{ - - /* USER CODE BEGIN UART5_Init 0 */ - - /* USER CODE END UART5_Init 0 */ - - /* USER CODE BEGIN UART5_Init 1 */ - - /* USER CODE END UART5_Init 1 */ - huart5.Instance = UART5; - huart5.Init.BaudRate = 115200; - huart5.Init.WordLength = UART_WORDLENGTH_8B; - huart5.Init.StopBits = UART_STOPBITS_1; - huart5.Init.Parity = UART_PARITY_NONE; - huart5.Init.Mode = UART_MODE_TX_RX; - huart5.Init.HwFlowCtl = UART_HWCONTROL_NONE; - huart5.Init.OverSampling = UART_OVERSAMPLING_16; - huart5.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; - huart5.Init.ClockPrescaler = UART_PRESCALER_DIV1; - huart5.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; - if (HAL_UART_Init(&huart5) != HAL_OK) - { - Error_Handler(); - } - if (HAL_UARTEx_SetTxFifoThreshold(&huart5, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) - { - Error_Handler(); - } - if (HAL_UARTEx_SetRxFifoThreshold(&huart5, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) - { - Error_Handler(); - } - if (HAL_UARTEx_DisableFifoMode(&huart5) != HAL_OK) - { - Error_Handler(); - } - /* USER CODE BEGIN UART5_Init 2 */ - - /* USER CODE END UART5_Init 2 */ - -} - /** * @brief USART1 Initialization Function * @param None @@ -511,7 +315,7 @@ static void MX_USART1_UART_Init(void) /* USER CODE END USART1_Init 1 */ huart1.Instance = USART1; - huart1.Init.BaudRate = 115200; + huart1.Init.BaudRate = 9600; huart1.Init.WordLength = UART_WORDLENGTH_8B; huart1.Init.StopBits = UART_STOPBITS_1; huart1.Init.Parity = UART_PARITY_NONE; @@ -543,54 +347,6 @@ static void MX_USART1_UART_Init(void) } -/** - * @brief USART2 Initialization Function - * @param None - * @retval None - */ -static void MX_USART2_UART_Init(void) -{ - - /* USER CODE BEGIN USART2_Init 0 */ - - /* USER CODE END USART2_Init 0 */ - - /* USER CODE BEGIN USART2_Init 1 */ - - /* USER CODE END USART2_Init 1 */ - huart2.Instance = USART2; - huart2.Init.BaudRate = 115200; - huart2.Init.WordLength = UART_WORDLENGTH_8B; - huart2.Init.StopBits = UART_STOPBITS_1; - huart2.Init.Parity = UART_PARITY_NONE; - huart2.Init.Mode = UART_MODE_TX_RX; - huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE; - huart2.Init.OverSampling = UART_OVERSAMPLING_16; - huart2.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; - huart2.Init.ClockPrescaler = UART_PRESCALER_DIV1; - huart2.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; - if (HAL_UART_Init(&huart2) != HAL_OK) - { - Error_Handler(); - } - if (HAL_UARTEx_SetTxFifoThreshold(&huart2, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) - { - Error_Handler(); - } - if (HAL_UARTEx_SetRxFifoThreshold(&huart2, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) - { - Error_Handler(); - } - if (HAL_UARTEx_DisableFifoMode(&huart2) != HAL_OK) - { - Error_Handler(); - } - /* USER CODE BEGIN USART2_Init 2 */ - - /* USER CODE END USART2_Init 2 */ - -} - /** * @brief USART3 Initialization Function * @param None @@ -607,7 +363,7 @@ static void MX_USART3_UART_Init(void) /* USER CODE END USART3_Init 1 */ huart3.Instance = USART3; - huart3.Init.BaudRate = 115200; + huart3.Init.BaudRate = 9600; huart3.Init.WordLength = UART_WORDLENGTH_8B; huart3.Init.StopBits = UART_STOPBITS_1; huart3.Init.Parity = UART_PARITY_NONE; @@ -639,54 +395,6 @@ static void MX_USART3_UART_Init(void) } -/** - * @brief USART6 Initialization Function - * @param None - * @retval None - */ -static void MX_USART6_UART_Init(void) -{ - - /* USER CODE BEGIN USART6_Init 0 */ - - /* USER CODE END USART6_Init 0 */ - - /* USER CODE BEGIN USART6_Init 1 */ - - /* USER CODE END USART6_Init 1 */ - huart6.Instance = USART6; - huart6.Init.BaudRate = 115200; - huart6.Init.WordLength = UART_WORDLENGTH_8B; - huart6.Init.StopBits = UART_STOPBITS_1; - huart6.Init.Parity = UART_PARITY_NONE; - huart6.Init.Mode = UART_MODE_TX_RX; - huart6.Init.HwFlowCtl = UART_HWCONTROL_NONE; - huart6.Init.OverSampling = UART_OVERSAMPLING_16; - huart6.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; - huart6.Init.ClockPrescaler = UART_PRESCALER_DIV1; - huart6.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; - if (HAL_UART_Init(&huart6) != HAL_OK) - { - Error_Handler(); - } - if (HAL_UARTEx_SetTxFifoThreshold(&huart6, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) - { - Error_Handler(); - } - if (HAL_UARTEx_SetRxFifoThreshold(&huart6, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) - { - Error_Handler(); - } - if (HAL_UARTEx_DisableFifoMode(&huart6) != HAL_OK) - { - Error_Handler(); - } - /* USER CODE BEGIN USART6_Init 2 */ - - /* USER CODE END USART6_Init 2 */ - -} - /** * @brief GPIO Initialization Function * @param None @@ -700,9 +408,8 @@ static void MX_GPIO_Init(void) /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOH_CLK_ENABLE(); - __HAL_RCC_GPIOA_CLK_ENABLE(); - __HAL_RCC_GPIOC_CLK_ENABLE(); __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOA_CLK_ENABLE(); /* USER CODE BEGIN MX_GPIO_Init_2 */ diff --git a/bpdt-firmware/bpdt-adapter-stm32h5/Core/Src/stm32h5xx_hal_msp.c b/bpdt-firmware/bpdt-adapter-stm32h5/Core/Src/stm32h5xx_hal_msp.c index 0ba3784..a1184a0 100644 --- a/bpdt-firmware/bpdt-adapter-stm32h5/Core/Src/stm32h5xx_hal_msp.c +++ b/bpdt-firmware/bpdt-adapter-stm32h5/Core/Src/stm32h5xx_hal_msp.c @@ -73,8 +73,6 @@ void HAL_MspInit(void) /* USER CODE END MspInit 1 */ } -static uint32_t HAL_RCC_FDCAN_CLK_ENABLED=0; - /** * @brief FDCAN MSP Initialization * This function configures the hardware resources used in this example @@ -94,17 +92,14 @@ void HAL_FDCAN_MspInit(FDCAN_HandleTypeDef* hfdcan) /** Initializes the peripherals clock */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_FDCAN; - PeriphClkInitStruct.FdcanClockSelection = RCC_FDCANCLKSOURCE_HSE; + PeriphClkInitStruct.FdcanClockSelection = RCC_FDCANCLKSOURCE_PLL1Q; if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { Error_Handler(); } /* Peripheral clock enable */ - HAL_RCC_FDCAN_CLK_ENABLED++; - if(HAL_RCC_FDCAN_CLK_ENABLED==1){ - __HAL_RCC_FDCAN_CLK_ENABLE(); - } + __HAL_RCC_FDCAN_CLK_ENABLE(); __HAL_RCC_GPIOA_CLK_ENABLE(); /**FDCAN1 GPIO Configuration @@ -121,51 +116,7 @@ void HAL_FDCAN_MspInit(FDCAN_HandleTypeDef* hfdcan) /* USER CODE BEGIN FDCAN1_MspInit 1 */ /* USER CODE END FDCAN1_MspInit 1 */ - } - else if(hfdcan->Instance==FDCAN2) - { - /* USER CODE BEGIN FDCAN2_MspInit 0 */ - /* USER CODE END FDCAN2_MspInit 0 */ - - /** Initializes the peripherals clock - */ - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_FDCAN; - PeriphClkInitStruct.FdcanClockSelection = RCC_FDCANCLKSOURCE_HSE; - if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) - { - Error_Handler(); - } - - /* Peripheral clock enable */ - HAL_RCC_FDCAN_CLK_ENABLED++; - if(HAL_RCC_FDCAN_CLK_ENABLED==1){ - __HAL_RCC_FDCAN_CLK_ENABLE(); - } - - __HAL_RCC_GPIOA_CLK_ENABLE(); - __HAL_RCC_GPIOB_CLK_ENABLE(); - /**FDCAN2 GPIO Configuration - PA0 ------> FDCAN2_RX - PB13 ------> FDCAN2_TX - */ - GPIO_InitStruct.Pin = GPIO_PIN_0; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - GPIO_InitStruct.Alternate = GPIO_AF9_FDCAN2; - HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - GPIO_InitStruct.Pin = GPIO_PIN_13; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - GPIO_InitStruct.Alternate = GPIO_AF9_FDCAN2; - HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); - - /* USER CODE BEGIN FDCAN2_MspInit 1 */ - - /* USER CODE END FDCAN2_MspInit 1 */ } } @@ -184,10 +135,7 @@ void HAL_FDCAN_MspDeInit(FDCAN_HandleTypeDef* hfdcan) /* USER CODE END FDCAN1_MspDeInit 0 */ /* Peripheral clock disable */ - HAL_RCC_FDCAN_CLK_ENABLED--; - if(HAL_RCC_FDCAN_CLK_ENABLED==0){ - __HAL_RCC_FDCAN_CLK_DISABLE(); - } + __HAL_RCC_FDCAN_CLK_DISABLE(); /**FDCAN1 GPIO Configuration PA11 ------> FDCAN1_RX @@ -199,29 +147,6 @@ void HAL_FDCAN_MspDeInit(FDCAN_HandleTypeDef* hfdcan) /* USER CODE END FDCAN1_MspDeInit 1 */ } - else if(hfdcan->Instance==FDCAN2) - { - /* USER CODE BEGIN FDCAN2_MspDeInit 0 */ - - /* USER CODE END FDCAN2_MspDeInit 0 */ - /* Peripheral clock disable */ - HAL_RCC_FDCAN_CLK_ENABLED--; - if(HAL_RCC_FDCAN_CLK_ENABLED==0){ - __HAL_RCC_FDCAN_CLK_DISABLE(); - } - - /**FDCAN2 GPIO Configuration - PA0 ------> FDCAN2_RX - PB13 ------> FDCAN2_TX - */ - HAL_GPIO_DeInit(GPIOA, GPIO_PIN_0); - - HAL_GPIO_DeInit(GPIOB, GPIO_PIN_13); - - /* USER CODE BEGIN FDCAN2_MspDeInit 1 */ - - /* USER CODE END FDCAN2_MspDeInit 1 */ - } } @@ -235,91 +160,7 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) { GPIO_InitTypeDef GPIO_InitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; - if(huart->Instance==UART4) - { - /* USER CODE BEGIN UART4_MspInit 0 */ - - /* USER CODE END UART4_MspInit 0 */ - - /** Initializes the peripherals clock - */ - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_UART4; - PeriphClkInitStruct.Uart4ClockSelection = RCC_UART4CLKSOURCE_PCLK1; - if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) - { - Error_Handler(); - } - - /* Peripheral clock enable */ - __HAL_RCC_UART4_CLK_ENABLE(); - - __HAL_RCC_GPIOA_CLK_ENABLE(); - __HAL_RCC_GPIOC_CLK_ENABLE(); - /**UART4 GPIO Configuration - PA1 ------> UART4_RX - PC10 ------> UART4_TX - */ - GPIO_InitStruct.Pin = GPIO_PIN_1; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - GPIO_InitStruct.Alternate = GPIO_AF8_UART4; - HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - GPIO_InitStruct.Pin = GPIO_PIN_10; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - GPIO_InitStruct.Alternate = GPIO_AF8_UART4; - HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); - - /* USER CODE BEGIN UART4_MspInit 1 */ - - /* USER CODE END UART4_MspInit 1 */ - } - else if(huart->Instance==UART5) - { - /* USER CODE BEGIN UART5_MspInit 0 */ - - /* USER CODE END UART5_MspInit 0 */ - - /** Initializes the peripherals clock - */ - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_UART5; - PeriphClkInitStruct.Uart5ClockSelection = RCC_UART5CLKSOURCE_PCLK1; - if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) - { - Error_Handler(); - } - - /* Peripheral clock enable */ - __HAL_RCC_UART5_CLK_ENABLE(); - - __HAL_RCC_GPIOB_CLK_ENABLE(); - __HAL_RCC_GPIOC_CLK_ENABLE(); - /**UART5 GPIO Configuration - PB12 ------> UART5_RX - PC12 ------> UART5_TX - */ - GPIO_InitStruct.Pin = GPIO_PIN_12; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - GPIO_InitStruct.Alternate = GPIO_AF14_UART5; - HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); - - GPIO_InitStruct.Pin = GPIO_PIN_12; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - GPIO_InitStruct.Alternate = GPIO_AF8_UART5; - HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); - - /* USER CODE BEGIN UART5_MspInit 1 */ - - /* USER CODE END UART5_MspInit 1 */ - } - else if(huart->Instance==USART1) + if(huart->Instance==USART1) { /* USER CODE BEGIN USART1_MspInit 0 */ @@ -342,51 +183,27 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) PB14 ------> USART1_TX PB15 ------> USART1_RX */ - GPIO_InitStruct.Pin = GPIO_PIN_14|GPIO_PIN_15; + GPIO_InitStruct.Pin = GPIO_PIN_14; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF4_USART1; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_15; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; GPIO_InitStruct.Alternate = GPIO_AF4_USART1; HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + /* USART1 interrupt Init */ + HAL_NVIC_SetPriority(USART1_IRQn, 15, 0); + HAL_NVIC_EnableIRQ(USART1_IRQn); /* USER CODE BEGIN USART1_MspInit 1 */ /* USER CODE END USART1_MspInit 1 */ } - else if(huart->Instance==USART2) - { - /* USER CODE BEGIN USART2_MspInit 0 */ - - /* USER CODE END USART2_MspInit 0 */ - - /** Initializes the peripherals clock - */ - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART2; - PeriphClkInitStruct.Usart2ClockSelection = RCC_USART2CLKSOURCE_PCLK1; - if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) - { - Error_Handler(); - } - - /* Peripheral clock enable */ - __HAL_RCC_USART2_CLK_ENABLE(); - - __HAL_RCC_GPIOA_CLK_ENABLE(); - /**USART2 GPIO Configuration - PA2 ------> USART2_TX - PA3 ------> USART2_RX - */ - GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - GPIO_InitStruct.Alternate = GPIO_AF7_USART2; - HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - /* USER CODE BEGIN USART2_MspInit 1 */ - - /* USER CODE END USART2_MspInit 1 */ - } else if(huart->Instance==USART3) { /* USER CODE BEGIN USART3_MspInit 0 */ @@ -405,64 +222,25 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) /* Peripheral clock enable */ __HAL_RCC_USART3_CLK_ENABLE(); - __HAL_RCC_GPIOC_CLK_ENABLE(); __HAL_RCC_GPIOB_CLK_ENABLE(); /**USART3 GPIO Configuration - PC4 ------> USART3_RX + PB1 ------> USART3_RX PB10 ------> USART3_TX */ - GPIO_InitStruct.Pin = GPIO_PIN_4; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - GPIO_InitStruct.Alternate = GPIO_AF7_USART3; - HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); - - GPIO_InitStruct.Pin = GPIO_PIN_10; + GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_10; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; GPIO_InitStruct.Alternate = GPIO_AF7_USART3; HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + /* USART3 interrupt Init */ + HAL_NVIC_SetPriority(USART3_IRQn, 15, 0); + HAL_NVIC_EnableIRQ(USART3_IRQn); /* USER CODE BEGIN USART3_MspInit 1 */ /* USER CODE END USART3_MspInit 1 */ } - else if(huart->Instance==USART6) - { - /* USER CODE BEGIN USART6_MspInit 0 */ - - /* USER CODE END USART6_MspInit 0 */ - - /** Initializes the peripherals clock - */ - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART6; - PeriphClkInitStruct.Usart6ClockSelection = RCC_USART6CLKSOURCE_PCLK1; - if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) - { - Error_Handler(); - } - - /* Peripheral clock enable */ - __HAL_RCC_USART6_CLK_ENABLE(); - - __HAL_RCC_GPIOC_CLK_ENABLE(); - /**USART6 GPIO Configuration - PC6 ------> USART6_TX - PC7 ------> USART6_RX - */ - GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - GPIO_InitStruct.Alternate = GPIO_AF7_USART6; - HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); - - /* USER CODE BEGIN USART6_MspInit 1 */ - - /* USER CODE END USART6_MspInit 1 */ - } } @@ -474,47 +252,7 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) */ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) { - if(huart->Instance==UART4) - { - /* USER CODE BEGIN UART4_MspDeInit 0 */ - - /* USER CODE END UART4_MspDeInit 0 */ - /* Peripheral clock disable */ - __HAL_RCC_UART4_CLK_DISABLE(); - - /**UART4 GPIO Configuration - PA1 ------> UART4_RX - PC10 ------> UART4_TX - */ - HAL_GPIO_DeInit(GPIOA, GPIO_PIN_1); - - HAL_GPIO_DeInit(GPIOC, GPIO_PIN_10); - - /* USER CODE BEGIN UART4_MspDeInit 1 */ - - /* USER CODE END UART4_MspDeInit 1 */ - } - else if(huart->Instance==UART5) - { - /* USER CODE BEGIN UART5_MspDeInit 0 */ - - /* USER CODE END UART5_MspDeInit 0 */ - /* Peripheral clock disable */ - __HAL_RCC_UART5_CLK_DISABLE(); - - /**UART5 GPIO Configuration - PB12 ------> UART5_RX - PC12 ------> UART5_TX - */ - HAL_GPIO_DeInit(GPIOB, GPIO_PIN_12); - - HAL_GPIO_DeInit(GPIOC, GPIO_PIN_12); - - /* USER CODE BEGIN UART5_MspDeInit 1 */ - - /* USER CODE END UART5_MspDeInit 1 */ - } - else if(huart->Instance==USART1) + if(huart->Instance==USART1) { /* USER CODE BEGIN USART1_MspDeInit 0 */ @@ -528,28 +266,12 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) */ HAL_GPIO_DeInit(GPIOB, GPIO_PIN_14|GPIO_PIN_15); + /* USART1 interrupt DeInit */ + HAL_NVIC_DisableIRQ(USART1_IRQn); /* USER CODE BEGIN USART1_MspDeInit 1 */ /* USER CODE END USART1_MspDeInit 1 */ } - else if(huart->Instance==USART2) - { - /* USER CODE BEGIN USART2_MspDeInit 0 */ - - /* USER CODE END USART2_MspDeInit 0 */ - /* Peripheral clock disable */ - __HAL_RCC_USART2_CLK_DISABLE(); - - /**USART2 GPIO Configuration - PA2 ------> USART2_TX - PA3 ------> USART2_RX - */ - HAL_GPIO_DeInit(GPIOA, GPIO_PIN_2|GPIO_PIN_3); - - /* USER CODE BEGIN USART2_MspDeInit 1 */ - - /* USER CODE END USART2_MspDeInit 1 */ - } else if(huart->Instance==USART3) { /* USER CODE BEGIN USART3_MspDeInit 0 */ @@ -559,35 +281,17 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) __HAL_RCC_USART3_CLK_DISABLE(); /**USART3 GPIO Configuration - PC4 ------> USART3_RX + PB1 ------> USART3_RX PB10 ------> USART3_TX */ - HAL_GPIO_DeInit(GPIOC, GPIO_PIN_4); - - HAL_GPIO_DeInit(GPIOB, GPIO_PIN_10); + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_1|GPIO_PIN_10); + /* USART3 interrupt DeInit */ + HAL_NVIC_DisableIRQ(USART3_IRQn); /* USER CODE BEGIN USART3_MspDeInit 1 */ /* USER CODE END USART3_MspDeInit 1 */ } - else if(huart->Instance==USART6) - { - /* USER CODE BEGIN USART6_MspDeInit 0 */ - - /* USER CODE END USART6_MspDeInit 0 */ - /* Peripheral clock disable */ - __HAL_RCC_USART6_CLK_DISABLE(); - - /**USART6 GPIO Configuration - PC6 ------> USART6_TX - PC7 ------> USART6_RX - */ - HAL_GPIO_DeInit(GPIOC, GPIO_PIN_6|GPIO_PIN_7); - - /* USER CODE BEGIN USART6_MspDeInit 1 */ - - /* USER CODE END USART6_MspDeInit 1 */ - } } diff --git a/bpdt-firmware/bpdt-adapter-stm32h5/Core/Src/stm32h5xx_it.c b/bpdt-firmware/bpdt-adapter-stm32h5/Core/Src/stm32h5xx_it.c index f91f219..dbc8aa9 100644 --- a/bpdt-firmware/bpdt-adapter-stm32h5/Core/Src/stm32h5xx_it.c +++ b/bpdt-firmware/bpdt-adapter-stm32h5/Core/Src/stm32h5xx_it.c @@ -55,7 +55,8 @@ /* USER CODE END 0 */ /* External variables --------------------------------------------------------*/ - +extern UART_HandleTypeDef huart1; +extern UART_HandleTypeDef huart3; /* USER CODE BEGIN EV */ /* USER CODE END EV */ @@ -198,6 +199,34 @@ void SysTick_Handler(void) /* please refer to the startup file (startup_stm32h5xx.s). */ /******************************************************************************/ +/** + * @brief This function handles USART1 global interrupt. + */ +void USART1_IRQHandler(void) +{ + /* USER CODE BEGIN USART1_IRQn 0 */ + + /* USER CODE END USART1_IRQn 0 */ + HAL_UART_IRQHandler(&huart1); + /* USER CODE BEGIN USART1_IRQn 1 */ + + /* USER CODE END USART1_IRQn 1 */ +} + +/** + * @brief This function handles USART3 global interrupt. + */ +void USART3_IRQHandler(void) +{ + /* USER CODE BEGIN USART3_IRQn 0 */ + + /* USER CODE END USART3_IRQn 0 */ + HAL_UART_IRQHandler(&huart3); + /* USER CODE BEGIN USART3_IRQn 1 */ + + /* USER CODE END USART3_IRQn 1 */ +} + /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ diff --git a/bpdt-firmware/bpdt-adapter-stm32h5/Core/Startup/startup_stm32h533retx.s b/bpdt-firmware/bpdt-adapter-stm32h5/Core/Startup/startup_stm32h533ceux.s similarity index 100% rename from bpdt-firmware/bpdt-adapter-stm32h5/Core/Startup/startup_stm32h533retx.s rename to bpdt-firmware/bpdt-adapter-stm32h5/Core/Startup/startup_stm32h533ceux.s diff --git a/bpdt-firmware/bpdt-adapter-stm32h5/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_icache.h b/bpdt-firmware/bpdt-adapter-stm32h5/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_icache.h deleted file mode 100644 index 6ecd441..0000000 --- a/bpdt-firmware/bpdt-adapter-stm32h5/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_icache.h +++ /dev/null @@ -1,300 +0,0 @@ -/** - ****************************************************************************** - * @file stm32h5xx_hal_icache.h - * @author MCD Application Team - * @brief Header file of ICACHE HAL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2023 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion ------------------------------------*/ -#ifndef STM32H5xx_HAL_ICACHE_H -#define STM32H5xx_HAL_ICACHE_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes -----------------------------------------------------------------*/ -#include "stm32h5xx_hal_def.h" - -#if defined(ICACHE) -/** @addtogroup STM32H5xx_HAL_Driver - * @{ - */ - -/** @addtogroup ICACHE - * @{ - */ - -/* Exported types -----------------------------------------------------------*/ -#if defined(ICACHE_CRRx_REN) -/** @defgroup ICACHE_Exported_Types ICACHE Exported Types - * @{ - */ - -/** - * @brief HAL ICACHE region configuration structure definition - */ -typedef struct -{ - uint32_t BaseAddress; /*!< Configures the Base address of Region i to be remapped */ - - uint32_t RemapAddress; /*!< Configures the Remap address of Region i to be remapped */ - - uint32_t Size; /*!< Configures the Region size. - This parameter can be a value of @ref ICACHE_Region_Size */ - - uint32_t TrafficRoute; /*!< Selects the traffic route. - This parameter can be a value of @ref ICACHE_Traffic_Route */ - - uint32_t OutputBurstType; /*!< Selects the output burst type. - This parameter can be a value of @ref ICACHE_Output_Burst_Type */ -} ICACHE_RegionConfigTypeDef; -/** - * @} - */ -#endif /* ICACHE_CRRx_REN */ - -/* Exported constants -------------------------------------------------------*/ -/** @defgroup ICACHE_Exported_Constants ICACHE Exported Constants - * @{ - */ - -/** @defgroup ICACHE_WaysSelection Ways selection - * @{ - */ -#define ICACHE_1WAY 0UL /*!< 1-way cache (direct mapped cache) */ -#define ICACHE_2WAYS ICACHE_CR_WAYSEL /*!< 2-ways set associative cache (default) */ -/** - * @} - */ - -/** @defgroup ICACHE_Monitor_Type Monitor type - * @{ - */ -#define ICACHE_MONITOR_HIT_MISS (ICACHE_CR_HITMEN | ICACHE_CR_MISSMEN) /*!< Hit & Miss monitoring */ -#define ICACHE_MONITOR_HIT ICACHE_CR_HITMEN /*!< Hit monitoring */ -#define ICACHE_MONITOR_MISS ICACHE_CR_MISSMEN /*!< Miss monitoring */ -/** - * @} - */ - -#if defined(ICACHE_CRRx_REN) -/** @defgroup ICACHE_Region Remapped Region number - * @{ - */ -#define ICACHE_REGION_0 0UL /*!< Region 0 */ -#define ICACHE_REGION_1 1UL /*!< Region 1 */ -#define ICACHE_REGION_2 2UL /*!< Region 2 */ -#define ICACHE_REGION_3 3UL /*!< Region 3 */ -/** - * @} - */ - -/** @defgroup ICACHE_Region_Size Remapped Region size - * @{ - */ -#define ICACHE_REGIONSIZE_2MB 1UL /*!< Region size 2MB */ -#define ICACHE_REGIONSIZE_4MB 2UL /*!< Region size 4MB */ -#define ICACHE_REGIONSIZE_8MB 3UL /*!< Region size 8MB */ -#define ICACHE_REGIONSIZE_16MB 4UL /*!< Region size 16MB */ -#define ICACHE_REGIONSIZE_32MB 5UL /*!< Region size 32MB */ -#define ICACHE_REGIONSIZE_64MB 6UL /*!< Region size 64MB */ -#define ICACHE_REGIONSIZE_128MB 7UL /*!< Region size 128MB */ -/** - * @} - */ - -/** @defgroup ICACHE_Traffic_Route Remapped Traffic route - * @{ - */ -#define ICACHE_MASTER1_PORT 0UL /*!< Master1 port */ -#define ICACHE_MASTER2_PORT ICACHE_CRRx_MSTSEL /*!< Master2 port */ -/** - * @} - */ - -/** @defgroup ICACHE_Output_Burst_Type Remapped Output burst type - * @{ - */ -#define ICACHE_OUTPUT_BURST_WRAP 0UL /*!< WRAP */ -#define ICACHE_OUTPUT_BURST_INCR ICACHE_CRRx_HBURST /*!< INCR */ -/** - * @} - */ -#endif /* ICACHE_CRRx_REN */ - -/** @defgroup ICACHE_Interrupts Interrupts - * @{ - */ -#define ICACHE_IT_BUSYEND ICACHE_IER_BSYENDIE /*!< Busy end interrupt */ -#define ICACHE_IT_ERROR ICACHE_IER_ERRIE /*!< Cache error interrupt */ -/** - * @} - */ - -/** @defgroup ICACHE_Flags Flags - * @{ - */ -#define ICACHE_FLAG_BUSY ICACHE_SR_BUSYF /*!< Busy flag */ -#define ICACHE_FLAG_BUSYEND ICACHE_SR_BSYENDF /*!< Busy end flag */ -#define ICACHE_FLAG_ERROR ICACHE_SR_ERRF /*!< Cache error flag */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macros ----------------------------------------------------------*/ -/** @defgroup ICACHE_Exported_Macros ICACHE Exported Macros - * @{ - */ - -/** @defgroup ICACHE_Flags_Interrupts_Management Flags and Interrupts Management - * @brief macros to manage the specified ICACHE flags and interrupts. - * @{ - */ - -/** @brief Enable ICACHE interrupts. - * @param __INTERRUPT__ specifies the ICACHE interrupt sources to be enabled. - * This parameter can be any combination of the following values: - * @arg @ref ICACHE_IT_BUSYEND Busy end interrupt - * @arg @ref ICACHE_IT_ERROR Cache error interrupt - */ -#define __HAL_ICACHE_ENABLE_IT(__INTERRUPT__) SET_BIT(ICACHE->IER, (__INTERRUPT__)) - -/** @brief Disable ICACHE interrupts. - * @param __INTERRUPT__ specifies the ICACHE interrupt sources to be disabled. - * This parameter can be any combination of the following values: - * @arg @ref ICACHE_IT_BUSYEND Busy end interrupt - * @arg @ref ICACHE_IT_ERROR Cache error interrupt - */ -#define __HAL_ICACHE_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(ICACHE->IER, (__INTERRUPT__)) - -/** @brief Check whether the specified ICACHE interrupt source is enabled or not. - * @param __INTERRUPT__ specifies the ICACHE interrupt source to check. - * This parameter can be any combination of the following values: - * @arg @ref ICACHE_IT_BUSYEND Busy end interrupt - * @arg @ref ICACHE_IT_ERROR Cache error interrupt - * @retval The state of __INTERRUPT__ (0 or 1). - */ -#define __HAL_ICACHE_GET_IT_SOURCE(__INTERRUPT__) \ - ((READ_BIT(ICACHE->IER, (__INTERRUPT__)) == (__INTERRUPT__)) ? 1U : 0U) - -/** @brief Check whether the selected ICACHE flag is set or not. - * @param __FLAG__ specifies the flag to check. - * This parameter can be one of the following values: - * @arg @ref ICACHE_FLAG_BUSY Busy flag - * @arg @ref ICACHE_FLAG_BUSYEND Busy end flag - * @arg @ref ICACHE_FLAG_ERROR Cache error flag - * @retval The state of __FLAG__ (0 or 1). - */ -#define __HAL_ICACHE_GET_FLAG(__FLAG__) ((READ_BIT(ICACHE->SR, (__FLAG__)) != 0U) ? 1U : 0U) - -/** @brief Clear the selected ICACHE flags. - * @param __FLAG__ specifies the ICACHE flags to clear. - * This parameter can be any combination of the following values: - * @arg @ref ICACHE_FLAG_BUSYEND Busy end flag - * @arg @ref ICACHE_FLAG_ERROR Cache error flag - */ -#define __HAL_ICACHE_CLEAR_FLAG(__FLAG__) WRITE_REG(ICACHE->FCR, (__FLAG__)) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported functions -------------------------------------------------------*/ -/** @addtogroup ICACHE_Exported_Functions - * @{ - */ - -/** @addtogroup ICACHE_Exported_Functions_Group1 - * @brief Initialization and control functions - * @{ - */ -/* Peripheral Control functions **********************************************/ -HAL_StatusTypeDef HAL_ICACHE_Enable(void); -HAL_StatusTypeDef HAL_ICACHE_Disable(void); -uint32_t HAL_ICACHE_IsEnabled(void); -HAL_StatusTypeDef HAL_ICACHE_ConfigAssociativityMode(uint32_t AssociativityMode); -HAL_StatusTypeDef HAL_ICACHE_DeInit(void); - -/******* Invalidate in blocking mode (Polling) */ -HAL_StatusTypeDef HAL_ICACHE_Invalidate(void); -/******* Invalidate in non-blocking mode (Interrupt) */ -HAL_StatusTypeDef HAL_ICACHE_Invalidate_IT(void); -/******* Wait for Invalidate complete in blocking mode (Polling) */ -HAL_StatusTypeDef HAL_ICACHE_WaitForInvalidateComplete(void); - -/******* Performance instruction cache monitoring functions */ -HAL_StatusTypeDef HAL_ICACHE_Monitor_Start(uint32_t MonitorType); -HAL_StatusTypeDef HAL_ICACHE_Monitor_Stop(uint32_t MonitorType); -HAL_StatusTypeDef HAL_ICACHE_Monitor_Reset(uint32_t MonitorType); -uint32_t HAL_ICACHE_Monitor_GetHitValue(void); -uint32_t HAL_ICACHE_Monitor_GetMissValue(void); - -/** - * @} - */ - -/** @addtogroup ICACHE_Exported_Functions_Group2 - * @brief IRQ and callback functions - * @{ - */ -/******* IRQHandler and Callbacks used in non-blocking mode (Interrupt) */ -void HAL_ICACHE_IRQHandler(void); -void HAL_ICACHE_InvalidateCompleteCallback(void); -void HAL_ICACHE_ErrorCallback(void); - -/** - * @} - */ - -#if defined(ICACHE_CRRx_REN) -/** @addtogroup ICACHE_Exported_Functions_Group3 - * @brief Memory remapped regions functions - * @{ - */ -/******* Memory remapped regions functions */ -HAL_StatusTypeDef HAL_ICACHE_EnableRemapRegion(uint32_t Region, const ICACHE_RegionConfigTypeDef *const pRegionConfig); -HAL_StatusTypeDef HAL_ICACHE_DisableRemapRegion(uint32_t Region); - -/** - * @} - */ -#endif /* ICACHE_CRRx_REN */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -#endif /* ICACHE */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32H5xx_HAL_ICACHE_H */ diff --git a/bpdt-firmware/bpdt-adapter-stm32h5/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_icache.h b/bpdt-firmware/bpdt-adapter-stm32h5/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_icache.h deleted file mode 100644 index ce663d6..0000000 --- a/bpdt-firmware/bpdt-adapter-stm32h5/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_icache.h +++ /dev/null @@ -1,788 +0,0 @@ -/** - ****************************************************************************** - * @file stm32h5xx_ll_icache.h - * @author MCD Application Team - * @brief Header file of ICACHE LL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2023 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion ------------------------------------*/ -#ifndef STM32H5xx_LL_ICACHE_H -#define STM32H5xx_LL_ICACHE_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes -----------------------------------------------------------------*/ -#include "stm32h5xx.h" - -/** @addtogroup STM32H5xx_LL_Driver - * @{ - */ - -#if defined(ICACHE) - -/** @defgroup ICACHE_LL ICACHE - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/* Exported types ------------------------------------------------------------*/ -#if defined(ICACHE_CRRx_REN) -/** @defgroup ICACHE_LL_REGION_CONFIG ICACHE Exported Configuration structure - * @{ - */ - -/** - * @brief LL ICACHE region configuration structure definition - */ -typedef struct -{ - uint32_t BaseAddress; /*!< Configures the C-AHB base address to be remapped */ - - uint32_t RemapAddress; /*!< Configures the remap address to be remapped */ - - uint32_t Size; /*!< Configures the region size. - This parameter can be a value of @ref ICACHE_LL_EC_Region_Size */ - - uint32_t TrafficRoute; /*!< Selects the traffic route. - This parameter can be a value of @ref ICACHE_LL_EC_Traffic_Route */ - - uint32_t OutputBurstType; /*!< Selects the output burst type. - This parameter can be a value of @ref ICACHE_LL_EC_Output_Burst_Type */ -} LL_ICACHE_RegionTypeDef; - -/** - * @} - */ -#endif /* ICACHE_CRRx_REN */ - -/* Exported constants -------------------------------------------------------*/ -/** @defgroup ICACHE_LL_Exported_Constants ICACHE Exported Constants - * @{ - */ - -/** @defgroup ICACHE_LL_EC_WaysSelection Ways selection - * @{ - */ -#define LL_ICACHE_1WAY 0U /*!< 1-way cache (direct mapped cache) */ -#define LL_ICACHE_2WAYS ICACHE_CR_WAYSEL /*!< 2-ways set associative cache (default) */ -/** - * @} - */ - -/** @defgroup ICACHE_LL_EC_Monitor_Type Monitor type - * @{ - */ -#define LL_ICACHE_MONITOR_HIT ICACHE_CR_HITMEN /*!< Hit monitor counter */ -#define LL_ICACHE_MONITOR_MISS ICACHE_CR_MISSMEN /*!< Miss monitor counter */ -#define LL_ICACHE_MONITOR_ALL (ICACHE_CR_HITMEN | ICACHE_CR_MISSMEN) /*!< All monitors counters */ -/** - * @} - */ - -/** @defgroup ICACHE_LL_EC_GET_FLAG Get Flags Defines - * @brief Flags defines which can be used with LL_ICACHE_ReadReg function - * @{ - */ -#define LL_ICACHE_SR_BUSYF ICACHE_SR_BUSYF /*!< Busy flag */ -#define LL_ICACHE_SR_BSYENDF ICACHE_SR_BSYENDF /*!< Busy end flag */ -#define LL_ICACHE_SR_ERRF ICACHE_SR_ERRF /*!< Cache error flag */ -/** - * @} - */ - -/** @defgroup ICACHE_LL_EC_CLEAR_FLAG Clear Flags Defines - * @brief Flags defines which can be used with LL_ICACHE_WriteReg function - * @{ - */ -#define LL_ICACHE_FCR_CBSYENDF ICACHE_FCR_CBSYENDF /*!< Busy end flag */ -#define LL_ICACHE_FCR_CERRF ICACHE_FCR_CERRF /*!< Cache error flag */ -/** - * @} - */ - -/** @defgroup ICACHE_LL_EC_IT IT Defines - * @brief IT defines which can be used with LL_ICACHE_ReadReg and LL_ICACHE_WriteReg functions - * @{ - */ -#define LL_ICACHE_IER_BSYENDIE ICACHE_IER_BSYENDIE /*!< Busy end interrupt */ -#define LL_ICACHE_IER_ERRIE ICACHE_IER_ERRIE /*!< Cache error interrupt */ -/** - * @} - */ - -#if defined(ICACHE_CRRx_REN) -/** @defgroup ICACHE_LL_EC_Region Remapped Region number - * @{ - */ -#define LL_ICACHE_REGION_0 0U /*!< Region 0 */ -#define LL_ICACHE_REGION_1 1U /*!< Region 1 */ -#define LL_ICACHE_REGION_2 2U /*!< Region 2 */ -#define LL_ICACHE_REGION_3 3U /*!< Region 3 */ -/** - * @} - */ - -/** @defgroup ICACHE_LL_EC_Region_Size Remapped Region size - * @{ - */ -#define LL_ICACHE_REGIONSIZE_2MB 1U /*!< Region size 2MB */ -#define LL_ICACHE_REGIONSIZE_4MB 2U /*!< Region size 4MB */ -#define LL_ICACHE_REGIONSIZE_8MB 3U /*!< Region size 8MB */ -#define LL_ICACHE_REGIONSIZE_16MB 4U /*!< Region size 16MB */ -#define LL_ICACHE_REGIONSIZE_32MB 5U /*!< Region size 32MB */ -#define LL_ICACHE_REGIONSIZE_64MB 6U /*!< Region size 64MB */ -#define LL_ICACHE_REGIONSIZE_128MB 7U /*!< Region size 128MB */ -/** - * @} - */ - -/** @defgroup ICACHE_LL_EC_Traffic_Route Remapped Traffic route - * @{ - */ -#define LL_ICACHE_MASTER1_PORT 0U /*!< Master1 port */ -#define LL_ICACHE_MASTER2_PORT ICACHE_CRRx_MSTSEL /*!< Master2 port */ -/** - * @} - */ - -/** @defgroup ICACHE_LL_EC_Output_Burst_Type Remapped Output burst type - * @{ - */ -#define LL_ICACHE_OUTPUT_BURST_WRAP 0U /*!< WRAP */ -#define LL_ICACHE_OUTPUT_BURST_INCR ICACHE_CRRx_HBURST /*!< INCR */ -/** - * @} - */ -#endif /* ICACHE_CRRx_REN */ - -/** - * @} - */ - -/* Exported macros ----------------------------------------------------------*/ -/** @defgroup ICACHE_LL_Exported_Macros ICACHE Exported Macros - * @{ - */ - -/** @defgroup ICACHE_LL_EM_WRITE_READ Common write and read registers Macros - * @{ - */ - -/** - * @brief Write a value in ICACHE register - * @param __REG__ Register to be written - * @param __VALUE__ Value to be written in the register - * @retval None - */ -#define LL_ICACHE_WriteReg(__REG__, __VALUE__) WRITE_REG(ICACHE->__REG__, (__VALUE__)) - -/** - * @brief Read a value in ICACHE register - * @param __REG__ Register to be read - * @retval Register value - */ -#define LL_ICACHE_ReadReg(__REG__) READ_REG(ICACHE->__REG__) -/** - * @} - */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup ICACHE_LL_Exported_Functions ICACHE Exported Functions - * @{ - */ - -/** @defgroup ICACHE_LL_EF_Configuration Configuration - * @{ - */ - -/** - * @brief Enable the ICACHE. - * @rmtoll CR EN LL_ICACHE_Enable - * @retval None - */ -__STATIC_INLINE void LL_ICACHE_Enable(void) -{ - SET_BIT(ICACHE->CR, ICACHE_CR_EN); -} - -/** - * @brief Disable the ICACHE. - * @rmtoll CR EN LL_ICACHE_Disable - * @retval None - */ -__STATIC_INLINE void LL_ICACHE_Disable(void) -{ - CLEAR_BIT(ICACHE->CR, ICACHE_CR_EN); -} - -/** - * @brief Return if ICACHE is enabled or not. - * @rmtoll CR EN LL_ICACHE_IsEnabled - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ICACHE_IsEnabled(void) -{ - return ((READ_BIT(ICACHE->CR, ICACHE_CR_EN) == (ICACHE_CR_EN)) ? 1UL : 0UL); -} - -/** - * @brief Select the ICACHE operating mode. - * @rmtoll CR WAYSEL LL_ICACHE_SetMode - * @param Mode This parameter can be one of the following values: - * @arg @ref LL_ICACHE_1WAY - * @arg @ref LL_ICACHE_2WAYS - * @retval None - */ -__STATIC_INLINE void LL_ICACHE_SetMode(uint32_t Mode) -{ - MODIFY_REG(ICACHE->CR, ICACHE_CR_WAYSEL, Mode); -} - -/** - * @brief Get the selected ICACHE operating mode. - * @rmtoll CR WAYSEL LL_ICACHE_GetMode - * @retval Returned value can be one of the following values: - * @arg @ref LL_ICACHE_1WAY - * @arg @ref LL_ICACHE_2WAYS - */ -__STATIC_INLINE uint32_t LL_ICACHE_GetMode(void) -{ - return (READ_BIT(ICACHE->CR, ICACHE_CR_WAYSEL)); -} - -/** - * @brief Invalidate the ICACHE. - * @note Until the BSYEND flag is set, the cache is bypassed. - * @rmtoll CR CACHEINV LL_ICACHE_Invalidate - * @retval None - */ -__STATIC_INLINE void LL_ICACHE_Invalidate(void) -{ - SET_BIT(ICACHE->CR, ICACHE_CR_CACHEINV); -} - -/** - * @} - */ - -/** @defgroup ICACHE_LL_EF_Monitors Monitors - * @{ - */ - -/** - * @brief Enable the hit/miss monitor(s). - * @rmtoll CR HITMEN LL_ICACHE_EnableMonitors - * @rmtoll CR MISSMEN LL_ICACHE_EnableMonitors - * @param Monitors This parameter can be one or a combination of the following values: - * @arg @ref LL_ICACHE_MONITOR_HIT - * @arg @ref LL_ICACHE_MONITOR_MISS - * @arg @ref LL_ICACHE_MONITOR_ALL - * @retval None - */ -__STATIC_INLINE void LL_ICACHE_EnableMonitors(uint32_t Monitors) -{ - SET_BIT(ICACHE->CR, Monitors); -} - -/** - * @brief Disable the hit/miss monitor(s). - * @rmtoll CR HITMEN LL_ICACHE_DisableMonitors - * @rmtoll CR MISSMEN LL_ICACHE_DisableMonitors - * @param Monitors This parameter can be one or a combination of the following values: - * @arg @ref LL_ICACHE_MONITOR_HIT - * @arg @ref LL_ICACHE_MONITOR_MISS - * @arg @ref LL_ICACHE_MONITOR_ALL - * @retval None - */ -__STATIC_INLINE void LL_ICACHE_DisableMonitors(uint32_t Monitors) -{ - CLEAR_BIT(ICACHE->CR, Monitors); -} - -/** - * @brief Check if the monitor(s) is(are) enabled or disabled. - * @rmtoll CR HITMEN LL_ICACHE_IsEnabledMonitors - * @rmtoll CR MISSMEN LL_ICACHE_IsEnabledMonitors - * @param Monitors This parameter can be one or a combination of the following values: - * @arg @ref LL_ICACHE_MONITOR_HIT - * @arg @ref LL_ICACHE_MONITOR_MISS - * @arg @ref LL_ICACHE_MONITOR_ALL - * @retval State of parameter value (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ICACHE_IsEnabledMonitors(uint32_t Monitors) -{ - return ((READ_BIT(ICACHE->CR, Monitors) == (Monitors)) ? 1UL : 0UL); -} - -/** - * @brief Reset the hit/miss monitor(s). - * @rmtoll CR HITMRST LL_ICACHE_ResetMonitors - * @rmtoll CR MISSMRST LL_ICACHE_ResetMonitors - * @param Monitors This parameter can be one or a combination of the following values: - * @arg @ref LL_ICACHE_MONITOR_HIT - * @arg @ref LL_ICACHE_MONITOR_MISS - * @arg @ref LL_ICACHE_MONITOR_ALL - * @retval None - */ -__STATIC_INLINE void LL_ICACHE_ResetMonitors(uint32_t Monitors) -{ - /* Reset */ - SET_BIT(ICACHE->CR, (Monitors << 2U)); - /* Release reset */ - CLEAR_BIT(ICACHE->CR, (Monitors << 2U)); -} - -/** - * @brief Get the Hit monitor. - * @note Upon reaching the 32-bit maximum value, hit monitor does not wrap. - * @rmtoll HMONR HITMON LL_ICACHE_GetHitMonitor - * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF - */ -__STATIC_INLINE uint32_t LL_ICACHE_GetHitMonitor(void) -{ - return (ICACHE->HMONR); -} - -/** - * @brief Get the Miss monitor. - * @note Upon reaching the 16-bit maximum value, miss monitor does not wrap. - * @rmtoll MMONR MISSMON LL_ICACHE_GetMissMonitor - * @retval Value between Min_Data=0 and Max_Data=0xFFFF - */ -__STATIC_INLINE uint32_t LL_ICACHE_GetMissMonitor(void) -{ - return (ICACHE->MMONR); -} - -/** - * @} - */ - -/** @defgroup ICACHE_LL_EF_IT_Management IT_Management - * @{ - */ - -/** - * @brief Enable BSYEND interrupt. - * @rmtoll IER BSYENDIE LL_ICACHE_EnableIT_BSYEND - * @retval None - */ -__STATIC_INLINE void LL_ICACHE_EnableIT_BSYEND(void) -{ - SET_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE); -} - -/** - * @brief Disable BSYEND interrupt. - * @rmtoll IER BSYENDIE LL_ICACHE_DisableIT_BSYEND - * @retval None - */ -__STATIC_INLINE void LL_ICACHE_DisableIT_BSYEND(void) -{ - CLEAR_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE); -} - -/** - * @brief Check if the BSYEND Interrupt is enabled or disabled. - * @rmtoll IER BSYENDIE LL_ICACHE_IsEnabledIT_BSYEND - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ICACHE_IsEnabledIT_BSYEND(void) -{ - return ((READ_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE) == (ICACHE_IER_BSYENDIE)) ? 1UL : 0UL); -} - -/** - * @brief Enable ERR interrupt. - * @rmtoll IER ERRIE LL_ICACHE_EnableIT_ERR - * @retval None - */ -__STATIC_INLINE void LL_ICACHE_EnableIT_ERR(void) -{ - SET_BIT(ICACHE->IER, ICACHE_IER_ERRIE); -} - -/** - * @brief Disable ERR interrupt. - * @rmtoll IER ERRIE LL_ICACHE_DisableIT_ERR - * @retval None - */ -__STATIC_INLINE void LL_ICACHE_DisableIT_ERR(void) -{ - CLEAR_BIT(ICACHE->IER, ICACHE_IER_ERRIE); -} - -/** - * @brief Check if the ERR Interrupt is enabled or disabled. - * @rmtoll IER ERRIE LL_ICACHE_IsEnabledIT_ERR - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ICACHE_IsEnabledIT_ERR(void) -{ - return ((READ_BIT(ICACHE->IER, ICACHE_IER_ERRIE) == (ICACHE_IER_ERRIE)) ? 1UL : 0UL); -} - -/** - * @} - */ - -/** @defgroup ICACHE_LL_EF_FLAG_Management FLAG_Management - * @{ - */ - -/** - * @brief Indicate the status of an ongoing operation flag. - * @rmtoll SR BUSYF LL_ICACHE_IsActiveFlag_BUSY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ICACHE_IsActiveFlag_BUSY(void) -{ - return ((READ_BIT(ICACHE->SR, ICACHE_SR_BUSYF) == (ICACHE_SR_BUSYF)) ? 1UL : 0UL); -} - -/** - * @brief Indicate the status of an operation end flag. - * @rmtoll SR BSYEND LL_ICACHE_IsActiveFlag_BSYEND - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ICACHE_IsActiveFlag_BSYEND(void) -{ - return ((READ_BIT(ICACHE->SR, ICACHE_SR_BSYENDF) == (ICACHE_SR_BSYENDF)) ? 1UL : 0UL); -} - -/** - * @brief Indicate the status of an error flag. - * @rmtoll SR ERRF LL_ICACHE_IsActiveFlag_ERR - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ICACHE_IsActiveFlag_ERR(void) -{ - return ((READ_BIT(ICACHE->SR, ICACHE_SR_ERRF) == (ICACHE_SR_ERRF)) ? 1UL : 0UL); -} - -/** - * @brief Clear busy end of operation flag. - * @rmtoll FCR CBSYENDF LL_ICACHE_ClearFlag_BSYEND - * @retval None - */ -__STATIC_INLINE void LL_ICACHE_ClearFlag_BSYEND(void) -{ - WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF); -} - -/** - * @brief Clear error flag. - * @rmtoll FCR ERRF LL_ICACHE_ClearFlag_ERR - * @retval None - */ -__STATIC_INLINE void LL_ICACHE_ClearFlag_ERR(void) -{ - WRITE_REG(ICACHE->FCR, ICACHE_FCR_CERRF); -} - -/** - * @} - */ - -#if defined(ICACHE_CRRx_REN) -/** @defgroup ICACHE_LL_EF_REGION_Management REGION_Management - * @{ - */ - -/** - * @brief Enable the remapped memory region. - * @note The region must have been already configured. - * @rmtoll CRRx REN LL_ICACHE_EnableRegion - * @param Region This parameter can be one of the following values: - * @arg @ref LL_ICACHE_REGION_0 - * @arg @ref LL_ICACHE_REGION_1 - * @arg @ref LL_ICACHE_REGION_2 - * @arg @ref LL_ICACHE_REGION_3 - * @retval None - */ -__STATIC_INLINE void LL_ICACHE_EnableRegion(uint32_t Region) -{ - SET_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ - ICACHE_CRRx_REN); -} - -/** - * @brief Disable the remapped memory region. - * @rmtoll CRRx REN LL_ICACHE_DisableRegion - * @param Region This parameter can be one of the following values: - * @arg @ref LL_ICACHE_REGION_0 - * @arg @ref LL_ICACHE_REGION_1 - * @arg @ref LL_ICACHE_REGION_2 - * @arg @ref LL_ICACHE_REGION_3 - * @retval None - */ -__STATIC_INLINE void LL_ICACHE_DisableRegion(uint32_t Region) -{ - CLEAR_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ - ICACHE_CRRx_REN); -} - -/** - * @brief Return if remapped memory region is enabled or not. - * @rmtoll CRRx REN LL_ICACHE_IsEnabledRegion - * @param Region This parameter can be one of the following values: - * @arg @ref LL_ICACHE_REGION_0 - * @arg @ref LL_ICACHE_REGION_1 - * @arg @ref LL_ICACHE_REGION_2 - * @arg @ref LL_ICACHE_REGION_3 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ICACHE_IsEnabledRegion(uint32_t Region) -{ - return ((READ_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ - ICACHE_CRRx_REN) == (ICACHE_CRRx_REN)) ? 1UL : 0UL); -} - -/** - * @brief Select the memory remapped region base address. - * @note The useful bits depends on RSIZE as described in the Reference Manual. - * @rmtoll CRRx BASEADDR LL_ICACHE_SetRegionBaseAddress - * @param Region This parameter can be one of the following values: - * @arg @ref LL_ICACHE_REGION_0 - * @arg @ref LL_ICACHE_REGION_1 - * @arg @ref LL_ICACHE_REGION_2 - * @arg @ref LL_ICACHE_REGION_3 - * @param Address Alias address in the Code region - * @retval None - */ -__STATIC_INLINE void LL_ICACHE_SetRegionBaseAddress(uint32_t Region, uint32_t Address) -{ - MODIFY_REG(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ - ICACHE_CRRx_BASEADDR, ((Address & 0x1FFFFFFFU) >> 21U)); -} - -/** - * @brief Get the memory remapped region base address. - * @note The base address is the alias in the Code region. - * @note The useful bits depends on RSIZE as described in the Reference Manual. - * @rmtoll CRRx BASEADDR LL_ICACHE_GetRegionBaseAddress - * @param Region This parameter can be one of the following values: - * @arg @ref LL_ICACHE_REGION_0 - * @arg @ref LL_ICACHE_REGION_1 - * @arg @ref LL_ICACHE_REGION_2 - * @arg @ref LL_ICACHE_REGION_3 - * @retval Address Alias address in the Code region - */ -__STATIC_INLINE uint32_t LL_ICACHE_GetRegionBaseAddress(uint32_t Region) -{ - return (READ_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ - ICACHE_CRRx_BASEADDR) << 21U); -} - -/** - * @brief Select the memory remapped region address. - * @note The useful bits depends on RSIZE as described in the Reference Manual. - * @rmtoll CRRx REMAPADDR LL_ICACHE_SetRegionRemapAddress - * @param Region This parameter can be one of the following values: - * @arg @ref LL_ICACHE_REGION_0 - * @arg @ref LL_ICACHE_REGION_1 - * @arg @ref LL_ICACHE_REGION_2 - * @arg @ref LL_ICACHE_REGION_3 - * @param Address Memory address to remap - * @retval None - */ -__STATIC_INLINE void LL_ICACHE_SetRegionRemapAddress(uint32_t Region, uint32_t Address) -{ - MODIFY_REG(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ - ICACHE_CRRx_REMAPADDR, ((Address >> 21U) << ICACHE_CRRx_REMAPADDR_Pos)); -} - -/** - * @brief Get the memory remapped region address. - * @note The useful bits depends on RSIZE as described in the Reference Manual. - * @rmtoll CRRx REMAPADDR LL_ICACHE_GetRegionRemapAddress - * @param Region This parameter can be one of the following values: - * @arg @ref LL_ICACHE_REGION_0 - * @arg @ref LL_ICACHE_REGION_1 - * @arg @ref LL_ICACHE_REGION_2 - * @arg @ref LL_ICACHE_REGION_3 - * @retval Address Remapped memory address - */ -__STATIC_INLINE uint32_t LL_ICACHE_GetRegionRemapAddress(uint32_t Region) -{ - return ((READ_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ - ICACHE_CRRx_REMAPADDR) >> ICACHE_CRRx_REMAPADDR_Pos) << 21U); -} - -/** - * @brief Select the memory remapped region size. - * @rmtoll CRRx RSIZE LL_ICACHE_SetRegionSize - * @param Region This parameter can be one of the following values: - * @arg @ref LL_ICACHE_REGION_0 - * @arg @ref LL_ICACHE_REGION_1 - * @arg @ref LL_ICACHE_REGION_2 - * @arg @ref LL_ICACHE_REGION_3 - * @param Size This parameter can be one of the following values: - * @arg @ref LL_ICACHE_REGIONSIZE_2MB - * @arg @ref LL_ICACHE_REGIONSIZE_4MB - * @arg @ref LL_ICACHE_REGIONSIZE_8MB - * @arg @ref LL_ICACHE_REGIONSIZE_16MB - * @arg @ref LL_ICACHE_REGIONSIZE_32MB - * @arg @ref LL_ICACHE_REGIONSIZE_64MB - * @arg @ref LL_ICACHE_REGIONSIZE_128MB - * @retval None - */ -__STATIC_INLINE void LL_ICACHE_SetRegionSize(uint32_t Region, uint32_t Size) -{ - MODIFY_REG(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ - ICACHE_CRRx_RSIZE, (Size << ICACHE_CRRx_RSIZE_Pos)); -} - -/** - * @brief Get the selected the memory remapped region size. - * @rmtoll CRRx RSIZE LL_ICACHE_GetRegionSize - * @param Region This parameter can be one of the following values: - * @arg @ref LL_ICACHE_REGION_0 - * @arg @ref LL_ICACHE_REGION_1 - * @arg @ref LL_ICACHE_REGION_2 - * @arg @ref LL_ICACHE_REGION_3 - * @retval Returned value can be one of the following values: - * @arg @ref LL_ICACHE_REGIONSIZE_2MB - * @arg @ref LL_ICACHE_REGIONSIZE_4MB - * @arg @ref LL_ICACHE_REGIONSIZE_8MB - * @arg @ref LL_ICACHE_REGIONSIZE_16MB - * @arg @ref LL_ICACHE_REGIONSIZE_32MB - * @arg @ref LL_ICACHE_REGIONSIZE_64MB - * @arg @ref LL_ICACHE_REGIONSIZE_128MB - */ -__STATIC_INLINE uint32_t LL_ICACHE_GetRegionSize(uint32_t Region) -{ - return (READ_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ - ICACHE_CRRx_RSIZE) >> ICACHE_CRRx_RSIZE_Pos); -} - -/** - * @brief Select the memory remapped region output burst type. - * @rmtoll CRRx HBURST LL_ICACHE_SetRegionOutputBurstType - * @param Region This parameter can be one of the following values: - * @arg @ref LL_ICACHE_REGION_0 - * @arg @ref LL_ICACHE_REGION_1 - * @arg @ref LL_ICACHE_REGION_2 - * @arg @ref LL_ICACHE_REGION_3 - * @param Type This parameter can be one of the following values: - * @arg @ref LL_ICACHE_OUTPUT_BURST_WRAP - * @arg @ref LL_ICACHE_OUTPUT_BURST_INCR - * @retval None - */ -__STATIC_INLINE void LL_ICACHE_SetRegionOutputBurstType(uint32_t Region, uint32_t Type) -{ - MODIFY_REG(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ - ICACHE_CRRx_HBURST, Type); -} - -/** - * @brief Get the selected the memory remapped region output burst type. - * @rmtoll CRRx HBURST LL_ICACHE_GetRegionOutputBurstType - * @param Region This parameter can be one of the following values: - * @arg @ref LL_ICACHE_REGION_0 - * @arg @ref LL_ICACHE_REGION_1 - * @arg @ref LL_ICACHE_REGION_2 - * @arg @ref LL_ICACHE_REGION_3 - * @retval Returned value can be one of the following values: - * @arg @ref LL_ICACHE_OUTPUT_BURST_WRAP - * @arg @ref LL_ICACHE_OUTPUT_BURST_INCR - */ -__STATIC_INLINE uint32_t LL_ICACHE_GetRegionOutputBurstType(uint32_t Region) -{ - return (READ_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ - ICACHE_CRRx_HBURST)); -} - -/** - * @brief Select the memory remapped region cache master port. - * @rmtoll CRRx MSTSEL LL_ICACHE_SetRegionMasterPort - * @param Region This parameter can be one of the following values: - * @arg @ref LL_ICACHE_REGION_0 - * @arg @ref LL_ICACHE_REGION_1 - * @arg @ref LL_ICACHE_REGION_2 - * @arg @ref LL_ICACHE_REGION_3 - * @param Port This parameter can be one of the following values: - * @arg @ref LL_ICACHE_MASTER1_PORT - * @arg @ref LL_ICACHE_MASTER2_PORT - * @retval None - */ -__STATIC_INLINE void LL_ICACHE_SetRegionMasterPort(uint32_t Region, uint32_t Port) -{ - MODIFY_REG(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ - ICACHE_CRRx_MSTSEL, Port); -} - -/** - * @brief Get the selected the memory remapped region cache master port. - * @rmtoll CRRx MSTSEL LL_ICACHE_GetRegionMasterPort - * @param Region This parameter can be one of the following values: - * @arg @ref LL_ICACHE_REGION_0 - * @arg @ref LL_ICACHE_REGION_1 - * @arg @ref LL_ICACHE_REGION_2 - * @arg @ref LL_ICACHE_REGION_3 - * @retval Returned value can be one of the following values: - * @arg @ref LL_ICACHE_MASTER1_PORT - * @arg @ref LL_ICACHE_MASTER2_PORT - */ -__STATIC_INLINE uint32_t LL_ICACHE_GetRegionMasterPort(uint32_t Region) -{ - return (READ_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ - ICACHE_CRRx_MSTSEL)); -} - -/** - * @} - */ - -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup ICACHE_LL_EF_REGION_Init Region Initialization functions - * @{ - */ - -void LL_ICACHE_ConfigRegion(uint32_t Region, const LL_ICACHE_RegionTypeDef *const pICACHE_RegionStruct); - -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -#endif /* ICACHE_CRRx_REN */ -/** - * @} - */ - -/** - * @} - */ - -#endif /* ICACHE */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32H5xx_LL_ICACHE_H */ diff --git a/bpdt-firmware/bpdt-adapter-stm32h5/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_icache.c b/bpdt-firmware/bpdt-adapter-stm32h5/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_icache.c deleted file mode 100644 index 4ce76ea..0000000 --- a/bpdt-firmware/bpdt-adapter-stm32h5/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_icache.c +++ /dev/null @@ -1,657 +0,0 @@ -/** - ****************************************************************************** - * @file stm32h5xx_hal_icache.c - * @author MCD Application Team - * @brief ICACHE HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Instruction Cache (ICACHE). - * + Initialization and Configuration - * + Invalidate functions - * + Monitoring management - * + Memory address remap management - ****************************************************************************** - * @attention - * - * Copyright (c) 2023 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - ============================================================================== - ##### ICACHE main features ##### - ============================================================================== - [..] - The Instruction Cache (ICACHE) is introduced on C-AHB code bus of - Cortex-M33 processor to improve performance when fetching instruction - and data from both internal and external memories. It allows close to - zero wait states performance. - - (+) The ICACHE provides two performance counters (Hit and Miss), - cache invalidate maintenance operation, error management and TrustZone - security support. - - (+) The ICACHE provides additionally the possibility to remap input address - falling into up to four memory regions (used to remap aliased code in - external memories to the internal Code region, for execution) - - =============================================================================== - ##### How to use this driver ##### - =============================================================================== - [..] - The ICACHE HAL driver can be used as follows: - - (#) Optionally configure the Instruction Cache mode with - HAL_ICACHE_ConfigAssociativityMode() if the default configuration - does not suit the application requirements. - - (#) Enable and disable the Instruction Cache with respectively - HAL_ICACHE_Enable() and HAL_ICACHE_Disable(). - Use HAL_ICACHE_IsEnabled() to get the Instruction Cache status. - To ensure a deterministic cache behavior after power on, system reset or after - a call to @ref HAL_ICACHE_Disable(), the application must call - @ref HAL_ICACHE_WaitForInvalidateComplete(). Indeed on power on, system reset - or cache disable, an automatic cache invalidation procedure is launched and the - cache is bypassed until the operation completes. - - (#) Initiate the cache maintenance invalidation procedure with either - HAL_ICACHE_Invalidate() (blocking mode) or HAL_ICACHE_Invalidate_IT() - (interrupt mode). When interrupt mode is used, the callback function - HAL_ICACHE_InvalidateCompleteCallback() is called when the invalidate - procedure is complete. The function HAL_ICACHE_WaitForInvalidateComplete() - may be called to wait for the end of the invalidate procedure automatically - initiated when disabling the Instruction Cache with HAL_ICACHE_Disable(). - The cache operation is bypassed during the invalidation procedure. - - (#) Use the performance monitoring counters for Hit and Miss with the following - functions: HAL_ICACHE_Monitor_Start(), HAL_ICACHE_Monitor_Stop(), - HAL_ICACHE_Monitor_Reset(), HAL_ICACHE_Monitor_GetHitValue() and - HAL_ICACHE_Monitor_GetMissValue() - - (#) Enable and disable up to four regions to remap input address from external - memories to the internal Code region for execution with - HAL_ICACHE_EnableRemapRegion() and HAL_ICACHE_DisableRemapRegion() - - @endverbatim - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32h5xx_hal.h" - -/** @addtogroup STM32H5xx_HAL_Driver - * @{ - */ - -/** @defgroup ICACHE ICACHE - * @brief HAL ICACHE module driver - * @{ - */ -#if defined(ICACHE) && defined (HAL_ICACHE_MODULE_ENABLED) - -/* Private typedef -----------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/** @addtogroup ICACHE_Private_Constants ICACHE Private Constants - * @{ - */ -#define ICACHE_INVALIDATE_TIMEOUT_VALUE 1U /* 1ms */ -#define ICACHE_DISABLE_TIMEOUT_VALUE 1U /* 1ms */ - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup ICACHE_Private_Macros ICACHE Private Macros - * @{ - */ - -#define IS_ICACHE_ASSOCIATIVITY_MODE(__MODE__) (((__MODE__) == ICACHE_1WAY) || \ - ((__MODE__) == ICACHE_2WAYS)) - -#define IS_ICACHE_MONITOR_TYPE(__TYPE__) (((__TYPE__) == ICACHE_MONITOR_HIT_MISS) || \ - ((__TYPE__) == ICACHE_MONITOR_HIT) || \ - ((__TYPE__) == ICACHE_MONITOR_MISS)) - -#if defined(ICACHE_CRRx_REN) -#define IS_ICACHE_REGION_NUMBER(__NUMBER__) ((__NUMBER__) < 4U) - -#define IS_ICACHE_REGION_SIZE(__SIZE__) (((__SIZE__) == ICACHE_REGIONSIZE_2MB) || \ - ((__SIZE__) == ICACHE_REGIONSIZE_4MB) || \ - ((__SIZE__) == ICACHE_REGIONSIZE_8MB) || \ - ((__SIZE__) == ICACHE_REGIONSIZE_16MB) || \ - ((__SIZE__) == ICACHE_REGIONSIZE_32MB) || \ - ((__SIZE__) == ICACHE_REGIONSIZE_64MB) || \ - ((__SIZE__) == ICACHE_REGIONSIZE_128MB)) - -#define IS_ICACHE_REGION_TRAFFIC_ROUTE(__TRAFFICROUTE__) (((__TRAFFICROUTE__) == ICACHE_MASTER1_PORT) || \ - ((__TRAFFICROUTE__) == ICACHE_MASTER2_PORT)) - -#define IS_ICACHE_REGION_OUTPUT_BURST_TYPE(__OUTPUTBURSTTYPE_) (((__OUTPUTBURSTTYPE_) == ICACHE_OUTPUT_BURST_WRAP) || \ - ((__OUTPUTBURSTTYPE_) == ICACHE_OUTPUT_BURST_INCR)) - -#endif /* ICACHE_CRRx_REN */ -/** - * @} - */ - -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ - -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup ICACHE_Exported_Functions ICACHE Exported Functions - * @{ - */ - -/** @defgroup ICACHE_Exported_Functions_Group1 Initialization and control functions - * @brief Initialization and control functions - * - @verbatim - ============================================================================== - ##### Initialization and control functions ##### - ============================================================================== - [..] - This section provides functions allowing to initialize and control the - Instruction Cache (mode, invalidate procedure, performance counters). - @endverbatim - * @{ - */ - -/** - * @brief Configure the Instruction Cache cache associativity mode selection. - * @param AssociativityMode Associativity mode selection - * This parameter can be one of the following values: - * @arg ICACHE_1WAY 1-way cache (direct mapped cache) - * @arg ICACHE_2WAYS 2-ways set associative cache (default) - * @retval HAL status (HAL_OK/HAL_ERROR) - */ -HAL_StatusTypeDef HAL_ICACHE_ConfigAssociativityMode(uint32_t AssociativityMode) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_ICACHE_ASSOCIATIVITY_MODE(AssociativityMode)); - - /* Check cache is not enabled */ - if (READ_BIT(ICACHE->CR, ICACHE_CR_EN) != 0U) - { - status = HAL_ERROR; - } - else - { - MODIFY_REG(ICACHE->CR, ICACHE_CR_WAYSEL, AssociativityMode); - } - - return status; -} - -/** - * @brief DeInitialize the Instruction Cache. - * @retval HAL status (HAL_OK) - */ -HAL_StatusTypeDef HAL_ICACHE_DeInit(void) -{ - /* Reset interrupt enable value */ - WRITE_REG(ICACHE->IER, 0U); - - /* Clear any pending flags */ - WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF | ICACHE_FCR_CERRF); - - /* Disable cache then set default associative mode value */ - CLEAR_BIT(ICACHE->CR, ICACHE_CR_EN); - WRITE_REG(ICACHE->CR, ICACHE_CR_WAYSEL); - - /* Stop monitor and reset monitor values */ - CLEAR_BIT(ICACHE->CR, ICACHE_MONITOR_HIT_MISS); - SET_BIT(ICACHE->CR, (ICACHE_MONITOR_HIT_MISS << 2U)); - CLEAR_BIT(ICACHE->CR, (ICACHE_MONITOR_HIT_MISS << 2U)); - -#if defined(ICACHE_CRRx_REN) - /* Reset regions configuration values */ - WRITE_REG(ICACHE->CRR0, ICACHE_REGIONSIZE_2MB << ICACHE_CRRx_RSIZE_Pos); - WRITE_REG(ICACHE->CRR1, ICACHE_REGIONSIZE_2MB << ICACHE_CRRx_RSIZE_Pos); - WRITE_REG(ICACHE->CRR2, ICACHE_REGIONSIZE_2MB << ICACHE_CRRx_RSIZE_Pos); - WRITE_REG(ICACHE->CRR3, ICACHE_REGIONSIZE_2MB << ICACHE_CRRx_RSIZE_Pos); -#endif /* ICACHE_CRRx_REN */ - - return HAL_OK; -} - -/** - * @brief Enable the Instruction Cache. - * @note This function always returns HAL_OK even if there is any ongoing - * cache operation. The Instruction Cache is bypassed until the - * cache operation completes. - * @retval HAL status (HAL_OK) - */ -HAL_StatusTypeDef HAL_ICACHE_Enable(void) -{ - SET_BIT(ICACHE->CR, ICACHE_CR_EN); - - return HAL_OK; -} - -/** - * @brief Disable the Instruction Cache. - * @note This function waits for the cache being disabled but - * not for the end of the automatic cache invalidation procedure. - * @retval HAL status (HAL_OK/HAL_TIMEOUT) - */ -HAL_StatusTypeDef HAL_ICACHE_Disable(void) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t tickstart; - - /* Make sure BSYENDF is reset before to disable the instruction cache */ - /* as it automatically starts a cache invalidation procedure */ - WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF); - - CLEAR_BIT(ICACHE->CR, ICACHE_CR_EN); - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait for instruction cache being disabled */ - while (READ_BIT(ICACHE->CR, ICACHE_CR_EN) != 0U) - { - if ((HAL_GetTick() - tickstart) > ICACHE_DISABLE_TIMEOUT_VALUE) - { - /* New check to avoid false timeout detection in case of preemption */ - if (READ_BIT(ICACHE->CR, ICACHE_CR_EN) != 0U) - { - status = HAL_TIMEOUT; - break; - } - } - } - - return status; -} - -/** - * @brief Check whether the Instruction Cache is enabled or not. - * @retval Status (0: disabled, 1: enabled) - */ -uint32_t HAL_ICACHE_IsEnabled(void) -{ - return ((READ_BIT(ICACHE->CR, ICACHE_CR_EN) != 0U) ? 1UL : 0UL); -} - -/** - * @brief Invalidate the Instruction Cache. - * @note This function waits for the end of cache invalidation procedure - * and clears the associated BSYENDF flag. - * @retval HAL status (HAL_OK/HAL_ERROR/HAL_TIMEOUT) - */ -HAL_StatusTypeDef HAL_ICACHE_Invalidate(void) -{ - HAL_StatusTypeDef status; - - /* Check if no ongoing operation */ - if (READ_BIT(ICACHE->SR, ICACHE_SR_BUSYF) == 0U) - { - /* Launch cache invalidation */ - SET_BIT(ICACHE->CR, ICACHE_CR_CACHEINV); - } - - status = HAL_ICACHE_WaitForInvalidateComplete(); - - return status; -} - -/** - * @brief Invalidate the Instruction Cache with interrupt. - * @note This function launches cache invalidation and returns. - * User application shall resort to interrupt generation to check - * the end of the cache invalidation with the BSYENDF flag and the - * HAL_ICACHE_InvalidateCompleteCallback() callback. - * @retval HAL status (HAL_OK/HAL_ERROR) - */ -HAL_StatusTypeDef HAL_ICACHE_Invalidate_IT(void) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check no ongoing operation */ - if (READ_BIT(ICACHE->SR, ICACHE_SR_BUSYF) != 0U) - { - status = HAL_ERROR; - } - else - { - /* Make sure BSYENDF is reset before to start cache invalidation */ - WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF); - - /* Enable end of cache invalidation interrupt */ - SET_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE); - - /* Launch cache invalidation */ - SET_BIT(ICACHE->CR, ICACHE_CR_CACHEINV); - } - - return status; -} - -/** - * @brief Wait for the end of the Instruction Cache invalidate procedure. - * @note This function checks and clears the BSYENDF flag when set. - * @retval HAL status (HAL_OK/HAL_TIMEOUT) - */ -HAL_StatusTypeDef HAL_ICACHE_WaitForInvalidateComplete(void) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t tickstart; - - /* Check if ongoing invalidation operation */ - if (READ_BIT(ICACHE->SR, ICACHE_SR_BUSYF) != 0U) - { - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait for end of cache invalidation */ - while (READ_BIT(ICACHE->SR, ICACHE_SR_BSYENDF) == 0U) - { - if ((HAL_GetTick() - tickstart) > ICACHE_INVALIDATE_TIMEOUT_VALUE) - { - /* New check to avoid false timeout detection in case of preemption */ - if (READ_BIT(ICACHE->SR, ICACHE_SR_BSYENDF) == 0U) - { - status = HAL_TIMEOUT; - break; - } - } - } - } - - /* Clear BSYENDF */ - WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF); - - return status; -} - - -/** - * @brief Start the Instruction Cache performance monitoring. - * @param MonitorType Monitoring type - * This parameter can be one of the following values: - * @arg ICACHE_MONITOR_HIT_MISS Hit & Miss monitoring - * @arg ICACHE_MONITOR_HIT Hit monitoring - * @arg ICACHE_MONITOR_MISS Miss monitoring - * @retval HAL status (HAL_OK) - */ -HAL_StatusTypeDef HAL_ICACHE_Monitor_Start(uint32_t MonitorType) -{ - /* Check the parameters */ - assert_param(IS_ICACHE_MONITOR_TYPE(MonitorType)); - - SET_BIT(ICACHE->CR, MonitorType); - - return HAL_OK; -} - -/** - * @brief Stop the Instruction Cache performance monitoring. - * @note Stopping the monitoring does not reset the values. - * @param MonitorType Monitoring type - * This parameter can be one of the following values: - * @arg ICACHE_MONITOR_HIT_MISS Hit & Miss monitoring - * @arg ICACHE_MONITOR_HIT Hit monitoring - * @arg ICACHE_MONITOR_MISS Miss monitoring - * @retval HAL status (HAL_OK) - */ -HAL_StatusTypeDef HAL_ICACHE_Monitor_Stop(uint32_t MonitorType) -{ - /* Check the parameters */ - assert_param(IS_ICACHE_MONITOR_TYPE(MonitorType)); - - CLEAR_BIT(ICACHE->CR, MonitorType); - - return HAL_OK; -} - -/** - * @brief Reset the Instruction Cache performance monitoring values. - * @param MonitorType Monitoring type - * This parameter can be one of the following values: - * @arg ICACHE_MONITOR_HIT_MISS Hit & Miss monitoring - * @arg ICACHE_MONITOR_HIT Hit monitoring - * @arg ICACHE_MONITOR_MISS Miss monitoring - * @retval HAL status (HAL_OK) - */ -HAL_StatusTypeDef HAL_ICACHE_Monitor_Reset(uint32_t MonitorType) -{ - /* Check the parameters */ - assert_param(IS_ICACHE_MONITOR_TYPE(MonitorType)); - - /* Force/Release reset */ - SET_BIT(ICACHE->CR, (MonitorType << 2U)); - CLEAR_BIT(ICACHE->CR, (MonitorType << 2U)); - - return HAL_OK; -} - -/** - * @brief Get the Instruction Cache performance Hit monitoring value. - * @note Upon reaching the 32-bit maximum value, monitor does not wrap. - * @retval Hit monitoring value - */ -uint32_t HAL_ICACHE_Monitor_GetHitValue(void) -{ - return (ICACHE->HMONR); -} - -/** - * @brief Get the Instruction Cache performance Miss monitoring value. - * @note Upon reaching the 32-bit maximum value, monitor does not wrap. - * @retval Miss monitoring value - */ -uint32_t HAL_ICACHE_Monitor_GetMissValue(void) -{ - return (ICACHE->MMONR); -} - -/** - * @} - */ - -/** @defgroup ICACHE_Exported_Functions_Group2 IRQ and callback functions - * @brief IRQ and callback functions - * - @verbatim - ============================================================================== - ##### IRQ and callback functions ##### - ============================================================================== - [..] - This section provides functions allowing to handle ICACHE global interrupt - and the associated callback functions. - @endverbatim - * @{ - */ - -/** - * @brief Handle the Instruction Cache interrupt request. - * @note This function should be called under the ICACHE_IRQHandler(). - * @note This function respectively disables the interrupt and clears the - * flag of any pending flag before calling the associated user callback. - * @retval None - */ -void HAL_ICACHE_IRQHandler(void) -{ - /* Get current interrupt flags and interrupt sources value */ - uint32_t itflags = READ_REG(ICACHE->SR); - uint32_t itsources = READ_REG(ICACHE->IER); - - /* Check Instruction cache Error interrupt flag */ - if (((itflags & itsources) & ICACHE_FLAG_ERROR) != 0U) - { - /* Disable error interrupt */ - CLEAR_BIT(ICACHE->IER, ICACHE_IER_ERRIE); - - /* Clear ERR pending flag */ - WRITE_REG(ICACHE->FCR, ICACHE_FCR_CERRF); - - /* Instruction cache error interrupt user callback */ - HAL_ICACHE_ErrorCallback(); - } - - /* Check Instruction cache BusyEnd interrupt flag */ - if (((itflags & itsources) & ICACHE_FLAG_BUSYEND) != 0U) - { - /* Disable end of cache invalidation interrupt */ - CLEAR_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE); - - /* Clear BSYENDF pending flag */ - WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF); - - /* Instruction cache busyend interrupt user callback */ - HAL_ICACHE_InvalidateCompleteCallback(); - } -} - -/** - * @brief Cache invalidation complete callback. - */ -__weak void HAL_ICACHE_InvalidateCompleteCallback(void) -{ - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_ICACHE_InvalidateCompleteCallback() should be implemented in the user file - */ -} - -/** - * @brief Error callback. - */ -__weak void HAL_ICACHE_ErrorCallback(void) -{ - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_ICACHE_ErrorCallback() should be implemented in the user file - */ -} - -/** - * @} - */ - -#if defined(ICACHE_CRRx_REN) -/** @defgroup ICACHE_Exported_Functions_Group3 Memory remapped regions functions - * @brief Memory remapped regions functions - * - @verbatim - ============================================================================== - ##### Memory remapped regions functions ##### - ============================================================================== - [..] - This section provides functions allowing to manage the remapping of - external memories to internal Code for execution. - @endverbatim - * @{ - */ - -/** - * @brief Configure and enable a region for memory remapping. - * @note The Instruction Cache and the region must be disabled. - * @param Region Region number - This parameter can be a value of @arg @ref ICACHE_Region - * @param pRegionConfig Pointer to structure of ICACHE region configuration parameters - * @retval HAL status (HAL_OK/HAL_ERROR) - */ -HAL_StatusTypeDef HAL_ICACHE_EnableRemapRegion(uint32_t Region, const ICACHE_RegionConfigTypeDef *const pRegionConfig) -{ - HAL_StatusTypeDef status = HAL_OK; - __IO uint32_t *p_reg; - uint32_t value; - - /* Check the parameters */ - assert_param(IS_ICACHE_REGION_NUMBER(Region)); - assert_param(IS_ICACHE_REGION_SIZE(pRegionConfig->Size)); - assert_param(IS_ICACHE_REGION_TRAFFIC_ROUTE(pRegionConfig->TrafficRoute)); - assert_param(IS_ICACHE_REGION_OUTPUT_BURST_TYPE(pRegionConfig->OutputBurstType)); - - /* Check cache is not enabled */ - if (READ_BIT(ICACHE->CR, ICACHE_CR_EN) != 0U) - { - status = HAL_ERROR; - } - else - { - /* Get region control register address */ - p_reg = &(ICACHE->CRR0) + (1U * Region); - - /* Check region is not already enabled */ - if ((*p_reg & ICACHE_CRRx_REN) != 0U) - { - status = HAL_ERROR; - } - else - { - /* Region 2MB: BaseAddress size 8 bits, RemapAddress size 11 bits */ - /* Region 4MB: BaseAddress size 7 bits, RemapAddress size 10 bits */ - /* Region 8MB: BaseAddress size 6 bits, RemapAddress size 9 bits */ - /* Region 16MB: BaseAddress size 5 bits, RemapAddress size 8 bits */ - /* Region 32MB: BaseAddress size 4 bits, RemapAddress size 7 bits */ - /* Region 64MB: BaseAddress size 3 bits, RemapAddress size 6 bits */ - /* Region 128MB: BaseAddress size 2 bits, RemapAddress size 5 bits */ - value = ((pRegionConfig->BaseAddress & 0x1FFFFFFFU) >> 21U) & \ - (0xFFU & ~(pRegionConfig->Size - 1U)); - value |= ((pRegionConfig->RemapAddress >> 5U) & \ - ((uint32_t)(0x7FFU & ~(pRegionConfig->Size - 1U)) << ICACHE_CRRx_REMAPADDR_Pos)); - value |= (pRegionConfig->Size << ICACHE_CRRx_RSIZE_Pos) | pRegionConfig->TrafficRoute | \ - pRegionConfig->OutputBurstType; - *p_reg = (value | ICACHE_CRRx_REN); - } - } - - return status; -} - -/** - * @brief Disable the memory remapping for a predefined region. - * @param Region Region number - This parameter can be a value of @arg @ref ICACHE_Region - * @retval HAL status (HAL_OK/HAL_ERROR) - */ -HAL_StatusTypeDef HAL_ICACHE_DisableRemapRegion(uint32_t Region) -{ - HAL_StatusTypeDef status = HAL_OK; - __IO uint32_t *p_reg; - - /* Check the parameters */ - assert_param(IS_ICACHE_REGION_NUMBER(Region)); - - /* Check cache is not enabled */ - if (READ_BIT(ICACHE->CR, ICACHE_CR_EN) != 0U) - { - status = HAL_ERROR; - } - else - { - /* Get region control register address */ - p_reg = &(ICACHE->CRR0) + (1U * Region); - - *p_reg &= ~ICACHE_CRRx_REN; - } - - return status; -} - - -/** - * @} - */ -#endif /* ICACHE_CRRx_REN */ - -/** - * @} - */ - -#endif /* ICACHE && HAL_ICACHE_MODULE_ENABLED */ - -/** - * @} - */ - -/** - * @} - */ diff --git a/bpdt-firmware/bpdt-adapter-stm32h5/STM32H533RETX_FLASH.ld b/bpdt-firmware/bpdt-adapter-stm32h5/STM32H533CEUX_FLASH.ld similarity index 98% rename from bpdt-firmware/bpdt-adapter-stm32h5/STM32H533RETX_FLASH.ld rename to bpdt-firmware/bpdt-adapter-stm32h5/STM32H533CEUX_FLASH.ld index 7b2ff3e..eb3113e 100644 --- a/bpdt-firmware/bpdt-adapter-stm32h5/STM32H533RETX_FLASH.ld +++ b/bpdt-firmware/bpdt-adapter-stm32h5/STM32H533CEUX_FLASH.ld @@ -5,7 +5,7 @@ ** ** @author : Auto-generated by STM32CubeIDE ** -** Abstract : Linker script for NUCLEO-H533RE Board embedding STM32H533RETx Device from stm32h5 series +** @brief : Linker script for STM32H533CEUx Device from STM32H5 series ** 512KBytes FLASH ** 272KBytes RAM ** diff --git a/bpdt-firmware/bpdt-adapter-stm32h5/STM32H533RETX_RAM.ld b/bpdt-firmware/bpdt-adapter-stm32h5/STM32H533CEUX_RAM.ld similarity index 98% rename from bpdt-firmware/bpdt-adapter-stm32h5/STM32H533RETX_RAM.ld rename to bpdt-firmware/bpdt-adapter-stm32h5/STM32H533CEUX_RAM.ld index 1563465..f03cc7f 100644 --- a/bpdt-firmware/bpdt-adapter-stm32h5/STM32H533RETX_RAM.ld +++ b/bpdt-firmware/bpdt-adapter-stm32h5/STM32H533CEUX_RAM.ld @@ -5,7 +5,7 @@ ** ** @author : Auto-generated by STM32CubeIDE ** -** Abstract : Linker script for NUCLEO-H533RE Board embedding STM32H533RETx Device from stm32h5 series +** @brief : Linker script for STM32H533CEUx Device from STM32H5 series ** 512KBytes FLASH ** 272KBytes RAM ** diff --git a/bpdt-firmware/bpdt-adapter-stm32h5/bpdt-adapter-stm32h5.ioc b/bpdt-firmware/bpdt-adapter-stm32h5/bpdt-adapter-stm32h5.ioc index 67461aa..e579fea 100644 --- a/bpdt-firmware/bpdt-adapter-stm32h5/bpdt-adapter-stm32h5.ioc +++ b/bpdt-firmware/bpdt-adapter-stm32h5/bpdt-adapter-stm32h5.ioc @@ -2,85 +2,89 @@ BOOTPATH.BootPathName=LEGACY BOOTPATH.IPParameters=BootPathName BOOTPATH.UserSelectedBootPath=LEGACY -BSP_IP_NAME=NUCLEO-H533RE -CAD.formats= -CAD.pinconfig= -CAD.provider= +CAD.formats=[] +CAD.pinconfig=Dual +CAD.provider=Component Search Engine CORTEX_M33_NS.IPParameters=default_mode_Activation,Number-Cortex_Memory_Protection_Unit_Region0_OTP_RO_AREAS_Settings CORTEX_M33_NS.Number-Cortex_Memory_Protection_Unit_Region0_OTP_RO_AREAS_Settings=MPU_REGION_NUMBER0 CORTEX_M33_NS.default_mode_Activation=1 CORTEX_M33_NS.userName=CORTEX_M33 -FDCAN1.CalculateBaudRateNominal=520833 -FDCAN1.CalculateTimeBitNominal=1920 -FDCAN1.CalculateTimeQuantumNominal=640.0 +FDCAN1.CalculateBaudRateNominal=2500000 +FDCAN1.CalculateTimeBitNominal=400 +FDCAN1.CalculateTimeQuantumNominal=133.33333333333334 FDCAN1.IPParameters=CalculateTimeQuantumNominal,CalculateTimeBitNominal,CalculateBaudRateNominal -FDCAN2.CalculateBaudRateNominal=520833 -FDCAN2.CalculateTimeBitNominal=1920 -FDCAN2.CalculateTimeQuantumNominal=640.0 -FDCAN2.IPParameters=CalculateTimeQuantumNominal,CalculateTimeBitNominal,CalculateBaudRateNominal File.Version=6 GPIO.groupedBy=Group By Peripherals KeepUserPlacement=false -MMTAppRegionsCount=0 +MMTAppReg1.MEMORYMAP.AP=RW_priv_only +MMTAppReg1.MEMORYMAP.AppRegionName=RAM +MMTAppReg1.MEMORYMAP.ContextName=CortexM33 +MMTAppReg1.MEMORYMAP.CoreName=ARM Cortex-M33 +MMTAppReg1.MEMORYMAP.DefaultDataRegion=true +MMTAppReg1.MEMORYMAP.IPParameters=StartAddress,Size,CoreName,DefaultDataRegion,ContextName,Name,AP +MMTAppReg1.MEMORYMAP.Name=RAM +MMTAppReg1.MEMORYMAP.Size=278528 +MMTAppReg1.MEMORYMAP.StartAddress=0x20000000 +MMTAppReg2.MEMORYMAP.AppRegionName=RAM Reserved Alias Region +MMTAppReg2.MEMORYMAP.CoreName=ARM Cortex-M33 +MMTAppReg2.MEMORYMAP.DefaultDataRegion=false +MMTAppReg2.MEMORYMAP.IPParameters=StartAddress,Size,CoreName,DefaultDataRegion,ReservedRegion,Name +MMTAppReg2.MEMORYMAP.Name=RAM Reserved Alias Region +MMTAppReg2.MEMORYMAP.ReservedRegion=true +MMTAppReg2.MEMORYMAP.Size=278528 +MMTAppReg2.MEMORYMAP.StartAddress=0x0A000000 +MMTAppReg3.MEMORYMAP.AP=RO_priv_only +MMTAppReg3.MEMORYMAP.AppRegionName=FLASH +MMTAppReg3.MEMORYMAP.Cacheability=WTRA +MMTAppReg3.MEMORYMAP.ContextName=CortexM33 +MMTAppReg3.MEMORYMAP.CoreName=ARM Cortex-M33 +MMTAppReg3.MEMORYMAP.DefaultCodeRegion=true +MMTAppReg3.MEMORYMAP.DefaultDataRegion=false +MMTAppReg3.MEMORYMAP.IPParameters=StartAddress,Size,CoreName,DefaultDataRegion,MemType,ContextName,Name,AP,Cacheability,DefaultCodeRegion +MMTAppReg3.MEMORYMAP.MemType=ROM +MMTAppReg3.MEMORYMAP.Name=FLASH +MMTAppReg3.MEMORYMAP.Size=524288 +MMTAppReg3.MEMORYMAP.StartAddress=0x08000000 +MMTAppRegionsCount=3 MMTConfigApplied=false -MMTSectionSuffix=_Section -Mcu.CPN=STM32H533RET6 +MMTSectionSuffix= +Mcu.CPN=STM32H533CEU6 Mcu.ContextProject=TrustZoneDisabled Mcu.Family=STM32H5 Mcu.IP0=BOOTPATH Mcu.IP1=CORTEX_M33_NS -Mcu.IP10=SYS -Mcu.IP11=UART4 -Mcu.IP12=UART5 -Mcu.IP13=USART1 -Mcu.IP14=USART2 -Mcu.IP15=USART3 -Mcu.IP16=USART6 -Mcu.IP17=NUCLEO-H533RE +Mcu.IP10=USART3 Mcu.IP2=DEBUG Mcu.IP3=FDCAN1 -Mcu.IP4=FDCAN2 -Mcu.IP5=ICACHE -Mcu.IP6=MEMORYMAP -Mcu.IP7=NVIC -Mcu.IP8=PWR -Mcu.IP9=RCC -Mcu.IPNb=18 -Mcu.Name=STM32H533RETx -Mcu.Package=LQFP64 +Mcu.IP4=MEMORYMAP +Mcu.IP5=NVIC +Mcu.IP6=PWR +Mcu.IP7=RCC +Mcu.IP8=SYS +Mcu.IP9=USART1 +Mcu.IPNb=11 +Mcu.Name=STM32H533CEUx +Mcu.Package=UFQFPN48 Mcu.Pin0=PH0-OSC_IN(PH0) Mcu.Pin1=PH1-OSC_OUT(PH1) -Mcu.Pin10=PB14 -Mcu.Pin11=PB15 -Mcu.Pin12=PC6 -Mcu.Pin13=PC7 -Mcu.Pin14=PA11 -Mcu.Pin15=PA12 -Mcu.Pin16=PA13(JTMS/SWDIO) -Mcu.Pin17=PA14(JTCK/SWCLK) -Mcu.Pin18=PA15(JTDI) -Mcu.Pin19=PC10 -Mcu.Pin2=PA0 -Mcu.Pin20=PC12 -Mcu.Pin21=PB3(JTDO/TRACESWO) -Mcu.Pin22=VP_CORTEX_M33_NS_VS_Hclk -Mcu.Pin23=VP_ICACHE_VS_ICACHE -Mcu.Pin24=VP_PWR_VS_SECSignals -Mcu.Pin25=VP_PWR_VS_LPOM -Mcu.Pin26=VP_SYS_VS_Systick -Mcu.Pin27=VP_BOOTPATH_VS_BOOTPATH -Mcu.Pin28=VP_MEMORYMAP_VS_MEMORYMAP -Mcu.Pin3=PA1 -Mcu.Pin4=PA2 -Mcu.Pin5=PA3 -Mcu.Pin6=PC4 -Mcu.Pin7=PB10 -Mcu.Pin8=PB12 -Mcu.Pin9=PB13 -Mcu.PinsNb=29 +Mcu.Pin10=VP_CORTEX_M33_NS_VS_Hclk +Mcu.Pin11=VP_PWR_VS_SECSignals +Mcu.Pin12=VP_PWR_VS_LPOM +Mcu.Pin13=VP_SYS_VS_Systick +Mcu.Pin14=VP_BOOTPATH_VS_BOOTPATH +Mcu.Pin15=VP_MEMORYMAP_VS_MEMORYMAP +Mcu.Pin2=PB1 +Mcu.Pin3=PB10 +Mcu.Pin4=PB14 +Mcu.Pin5=PB15 +Mcu.Pin6=PA11 +Mcu.Pin7=PA12 +Mcu.Pin8=PA13(JTMS/SWDIO) +Mcu.Pin9=PA14(JTCK/SWCLK) +Mcu.PinsNb=16 Mcu.ThirdPartyNb=0 Mcu.UserConstants= -Mcu.UserName=STM32H533RETx +Mcu.UserName=STM32H533CEUx MxCube.Version=6.17.0 MxDb.Version=DB.6.0.170 NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false @@ -93,64 +97,32 @@ NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:true\:false\:true\:false +NVIC.USART1_IRQn=true\:15\:0\:true\:false\:true\:true\:true\:true +NVIC.USART3_IRQn=true\:15\:0\:true\:false\:true\:true\:true\:true NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false -PA0.Mode=FDCAN_Activate -PA0.Signal=FDCAN2_RX -PA1.Mode=Asynchronous -PA1.Signal=UART4_RX PA11.Mode=FDCAN_Activate PA11.Signal=FDCAN1_RX PA12.Mode=FDCAN_Activate PA12.Signal=FDCAN1_TX -PA13(JTMS/SWDIO).GPIOParameters=GPIO_Label -PA13(JTMS/SWDIO).GPIO_Label=SWDIO -PA13(JTMS/SWDIO).Locked=true PA13(JTMS/SWDIO).Mode=Serial_Wire PA13(JTMS/SWDIO).Signal=DEBUG_JTMS-SWDIO -PA14(JTCK/SWCLK).GPIOParameters=GPIO_Label -PA14(JTCK/SWCLK).GPIO_Label=SWCLK -PA14(JTCK/SWCLK).Locked=true PA14(JTCK/SWCLK).Mode=Serial_Wire PA14(JTCK/SWCLK).Signal=DEBUG_JTCK-SWCLK -PA15(JTDI).GPIOParameters=GPIO_Label -PA15(JTDI).GPIO_Label=JTDI -PA15(JTDI).Locked=true -PA15(JTDI).Signal=DEBUG_JTDI -PA2.Locked=true -PA2.Mode=Asynchronous -PA2.Signal=USART2_TX -PA3.Locked=true -PA3.Mode=Asynchronous -PA3.Signal=USART2_RX +PB1.Mode=Asynchronous +PB1.Signal=USART3_RX PB10.Mode=Asynchronous PB10.Signal=USART3_TX -PB12.Mode=Asynchronous -PB12.Signal=UART5_RX -PB13.Mode=FDCAN_Activate -PB13.Signal=FDCAN2_TX +PB14.GPIOParameters=GPIO_Speed +PB14.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH PB14.Mode=Asynchronous PB14.Signal=USART1_TX PB15.Mode=Asynchronous PB15.Signal=USART1_RX -PB3(JTDO/TRACESWO).GPIOParameters=GPIO_Label -PB3(JTDO/TRACESWO).GPIO_Label=SWO -PB3(JTDO/TRACESWO).Locked=true -PB3(JTDO/TRACESWO).Signal=DEBUG_JTDO-SWO -PC10.Mode=Asynchronous -PC10.Signal=UART4_TX -PC12.Mode=Asynchronous -PC12.Signal=UART5_TX -PC4.Mode=Asynchronous -PC4.Signal=USART3_RX -PC6.Mode=Asynchronous -PC6.Signal=USART6_TX -PC7.Mode=Asynchronous -PC7.Signal=USART6_RX PCC.Checker=false PCC.Display=Plot\: All Steps PCC.Line=STM32H5x3 -PCC.MCU=STM32H533RETx -PCC.PartNumber=STM32H533RETx +PCC.MCU=STM32H533CEUx +PCC.PartNumber=STM32H533CEUx PCC.Series=STM32H5 PCC.Temperature=25 PCC.Vdd=3.0 @@ -168,7 +140,7 @@ ProjectManager.CoupleFile=false ProjectManager.CustomerFirmwarePackage= ProjectManager.DefaultFWLocation=true ProjectManager.DeletePrevious=true -ProjectManager.DeviceId=STM32H533RETx +ProjectManager.DeviceId=STM32H533CEUx ProjectManager.FirmwarePackage=STM32Cube FW_H5 V1.6.0 ProjectManager.FreePins=false ProjectManager.FreePinsContext= @@ -191,86 +163,88 @@ ProjectManager.ToolChainLocation= ProjectManager.UAScriptAfterPath= ProjectManager.UAScriptBeforePath= ProjectManager.UnderRoot=true -ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_ICACHE_Init-ICACHE-false-HAL-true,4-MX_FDCAN1_Init-FDCAN1-false-HAL-true,5-MX_FDCAN2_Init-FDCAN2-false-HAL-true,6-MX_UART4_Init-UART4-false-HAL-true,7-MX_UART5_Init-UART5-false-HAL-true,8-MX_USART1_UART_Init-USART1-false-HAL-true,9-MX_USART2_UART_Init-USART2-false-HAL-true,10-MX_USART3_UART_Init-USART3-false-HAL-true,11-MX_USART6_UART_Init-USART6-false-HAL-true,0-MX_CORTEX_M33_NS_Init-CORTEX_M33_NS-false-HAL-true,0-MX_PWR_Init-PWR-false-HAL-true -RCC.ADCFreq_Value=32000000 -RCC.AHBFreq_Value=32000000 -RCC.APB1Freq_Value=32000000 -RCC.APB1TimFreq_Value=32000000 -RCC.APB2Freq_Value=32000000 -RCC.APB2TimFreq_Value=32000000 -RCC.APB3Freq_Value=32000000 +ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_FDCAN1_Init-FDCAN1-false-HAL-true,4-MX_USART1_UART_Init-USART1-false-HAL-true,5-MX_USART3_UART_Init-USART3-false-HAL-true,0-MX_CORTEX_M33_NS_Init-CORTEX_M33_NS-false-HAL-true,0-MX_PWR_Init-PWR-false-HAL-true +RCC.ADCFreq_Value=120000000 +RCC.AHBFreq_Value=120000000 +RCC.APB1Freq_Value=120000000 +RCC.APB1TimFreq_Value=120000000 +RCC.APB2Freq_Value=120000000 +RCC.APB2TimFreq_Value=120000000 +RCC.APB3Freq_Value=120000000 RCC.CKPERFreq_Value=32000000 RCC.CRSFreq_Value=48000000 RCC.CSI_VALUE=4000000 -RCC.CortexFreq_Value=32000000 +RCC.CortexFreq_Value=120000000 RCC.DACFreq_Value=32768 -RCC.EPOD_VALUE=4000000 -RCC.FCLKCortexFreq_Value=32000000 -RCC.FDCANFreq_Value=25000000 +RCC.EPOD_VALUE=24000000 +RCC.FCLKCortexFreq_Value=120000000 +RCC.FDCANClockSelection=RCC_FDCANCLKSOURCE_PLL1Q +RCC.FDCANFreq_Value=120000000 RCC.FamilyName=M -RCC.HCLKFreq_Value=32000000 -RCC.HSE_VALUE=25000000 +RCC.HCLKFreq_Value=120000000 +RCC.HSE_VALUE=24000000 RCC.HSI48_VALUE=48000000 RCC.HSI_VALUE=64000000 -RCC.I2C1Freq_Value=32000000 -RCC.I2C2Freq_Value=32000000 -RCC.I2C3Freq_Value=32000000 -RCC.I3C1Freq_Value=32000000 -RCC.I3C2Freq_Value=32000000 -RCC.IPParameters=ADCFreq_Value,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CKPERFreq_Value,CRSFreq_Value,CSI_VALUE,CortexFreq_Value,DACFreq_Value,EPOD_VALUE,FCLKCortexFreq_Value,FDCANFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2C3Freq_Value,I3C1Freq_Value,I3C2Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSIRC_VALUE,MCO1PinFreq_Value,MCO2PinFreq_Value,OCTOSPIMFreq_Value,PLL2PoutputFreq_Value,PLL2QoutputFreq_Value,PLL2RoutputFreq_Value,PLL3PoutputFreq_Value,PLL3QoutputFreq_Value,PLL3RoutputFreq_Value,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PWRFreq_Value,RNGFreq_Value,SDMMC1Freq_Value,SPI1Freq_Value,SPI2Freq_Value,SPI3Freq_Value,SPI4Freq_Value,SYSCLKFreq_VALUE,UART4Freq_Value,UART5Freq_Value,UCPD1outputFreq_Value,USART1Freq_Value,USART2Freq_Value,USART3Freq_Value,USART6Freq_Value,USBFreq_Value,VCOInput2Freq_Value,VCOInput3Freq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOPLL2OutputFreq_Value,VCOPLL3OutputFreq_Value -RCC.LPTIM1Freq_Value=32000000 -RCC.LPTIM2Freq_Value=32000000 -RCC.LPUART1Freq_Value=32000000 +RCC.I2C1Freq_Value=120000000 +RCC.I2C2Freq_Value=120000000 +RCC.I2C3Freq_Value=120000000 +RCC.I3C1Freq_Value=120000000 +RCC.I3C2Freq_Value=120000000 +RCC.IPParameters=ADCFreq_Value,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CKPERFreq_Value,CRSFreq_Value,CSI_VALUE,CortexFreq_Value,DACFreq_Value,EPOD_VALUE,FCLKCortexFreq_Value,FDCANClockSelection,FDCANFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2C3Freq_Value,I3C1Freq_Value,I3C2Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSIRC_VALUE,MCO1PinFreq_Value,OCTOSPIMFreq_Value,PLL2FRACN,PLL2PoutputFreq_Value,PLL2QoutputFreq_Value,PLL2RoutputFreq_Value,PLL3FRACN,PLL3PoutputFreq_Value,PLL3QoutputFreq_Value,PLL3RoutputFreq_Value,PLLFRACN,PLLM,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLSourceVirtual,PWRFreq_Value,RNGFreq_Value,SPI1Freq_Value,SPI2Freq_Value,SPI3Freq_Value,SPI4Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,UART4Freq_Value,UART5Freq_Value,UCPD1outputFreq_Value,USART1Freq_Value,USART2Freq_Value,USART3Freq_Value,USBFreq_Value,VCOInput2Freq_Value,VCOInput3Freq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOPLL2OutputFreq_Value,VCOPLL3OutputFreq_Value,rccPrivilegeNSecure +RCC.LPTIM1Freq_Value=120000000 +RCC.LPTIM2Freq_Value=120000000 +RCC.LPUART1Freq_Value=120000000 RCC.LSCOPinFreq_Value=32000 RCC.LSE_VALUE=32768 RCC.LSIRC_VALUE=32000 RCC.MCO1PinFreq_Value=32000000 -RCC.MCO2PinFreq_Value=32000000 -RCC.OCTOSPIMFreq_Value=32000000 +RCC.OCTOSPIMFreq_Value=120000000 +RCC.PLL2FRACN=0 RCC.PLL2PoutputFreq_Value=258000000 RCC.PLL2QoutputFreq_Value=258000000 RCC.PLL2RoutputFreq_Value=258000000 +RCC.PLL3FRACN=0 RCC.PLL3PoutputFreq_Value=258000000 RCC.PLL3QoutputFreq_Value=258000000 RCC.PLL3RoutputFreq_Value=258000000 -RCC.PLLPoutputFreq_Value=258000000 -RCC.PLLQoutputFreq_Value=258000000 -RCC.PWRFreq_Value=32000000 +RCC.PLLFRACN=0 +RCC.PLLM=2 +RCC.PLLN=20 +RCC.PLLPoutputFreq_Value=120000000 +RCC.PLLQoutputFreq_Value=120000000 +RCC.PLLSourceVirtual=RCC_PLL1_SOURCE_HSE +RCC.PWRFreq_Value=120000000 RCC.RNGFreq_Value=48000000 -RCC.SDMMC1Freq_Value=258000000 -RCC.SPI1Freq_Value=258000000 -RCC.SPI2Freq_Value=258000000 -RCC.SPI3Freq_Value=258000000 -RCC.SPI4Freq_Value=32000000 -RCC.SYSCLKFreq_VALUE=32000000 -RCC.UART4Freq_Value=32000000 -RCC.UART5Freq_Value=32000000 +RCC.SPI1Freq_Value=120000000 +RCC.SPI2Freq_Value=120000000 +RCC.SPI3Freq_Value=120000000 +RCC.SPI4Freq_Value=120000000 +RCC.SYSCLKFreq_VALUE=120000000 +RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK +RCC.UART4Freq_Value=120000000 +RCC.UART5Freq_Value=120000000 RCC.UCPD1outputFreq_Value=8000000 -RCC.USART1Freq_Value=32000000 -RCC.USART2Freq_Value=32000000 -RCC.USART3Freq_Value=32000000 -RCC.USART6Freq_Value=32000000 +RCC.USART1Freq_Value=120000000 +RCC.USART2Freq_Value=120000000 +RCC.USART3Freq_Value=120000000 RCC.USBFreq_Value=48000000 RCC.VCOInput2Freq_Value=4000000 RCC.VCOInput3Freq_Value=4000000 -RCC.VCOInputFreq_Value=4000000 -RCC.VCOOutputFreq_Value=516000000 +RCC.VCOInputFreq_Value=12000000 +RCC.VCOOutputFreq_Value=240000000 RCC.VCOPLL2OutputFreq_Value=516000000 RCC.VCOPLL3OutputFreq_Value=516000000 -USART1.IPParameters=VirtualMode-Asynchronous +RCC.rccPrivilegeNSecure=RCC_NSEC_NPRIV +USART1.BaudRate=9600 +USART1.IPParameters=VirtualMode-Asynchronous,BaudRate USART1.VirtualMode-Asynchronous=VM_ASYNC -USART2.IPParameters=VirtualMode-Asynchronous -USART2.VirtualMode-Asynchronous=VM_ASYNC -USART3.IPParameters=VirtualMode-Asynchronous +USART3.BaudRate=9600 +USART3.IPParameters=VirtualMode-Asynchronous,BaudRate USART3.VirtualMode-Asynchronous=VM_ASYNC -USART6.IPParameters=VirtualMode -USART6.VirtualMode=VM_ASYNC VP_BOOTPATH_VS_BOOTPATH.Mode=BP_Activate VP_BOOTPATH_VS_BOOTPATH.Signal=BOOTPATH_VS_BOOTPATH VP_CORTEX_M33_NS_VS_Hclk.Mode=Hclk_Mode VP_CORTEX_M33_NS_VS_Hclk.Signal=CORTEX_M33_NS_VS_Hclk -VP_ICACHE_VS_ICACHE.Mode=DirectMappedCache -VP_ICACHE_VS_ICACHE.Signal=ICACHE_VS_ICACHE VP_MEMORYMAP_VS_MEMORYMAP.Mode=CurAppReg VP_MEMORYMAP_VS_MEMORYMAP.Signal=MEMORYMAP_VS_MEMORYMAP VP_PWR_VS_LPOM.Mode=PowerOptimisation @@ -279,5 +253,4 @@ VP_PWR_VS_SECSignals.Mode=Security/Privilege VP_PWR_VS_SECSignals.Signal=PWR_VS_SECSignals VP_SYS_VS_Systick.Mode=SysTick VP_SYS_VS_Systick.Signal=SYS_VS_Systick -board=NUCLEO-H533RE -boardIOC=true +board=custom