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Initial STM32H5 CubeMX/CubeIDE generated baseline

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LucianoDev
2026-03-26 17:32:19 +01:00
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/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file : main.h
* @brief : Header for main.c file.
* This file contains the common defines of the application.
******************************************************************************
* @attention
*
* Copyright (c) 2026 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __MAIN_H
#define __MAIN_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h5xx_hal.h"
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
/* Exported types ------------------------------------------------------------*/
/* USER CODE BEGIN ET */
/* USER CODE END ET */
/* Exported constants --------------------------------------------------------*/
/* USER CODE BEGIN EC */
/* USER CODE END EC */
/* Exported macro ------------------------------------------------------------*/
/* USER CODE BEGIN EM */
/* USER CODE END EM */
/* Exported functions prototypes ---------------------------------------------*/
void Error_Handler(void);
/* USER CODE BEGIN EFP */
/* USER CODE END EFP */
/* Private defines -----------------------------------------------------------*/
#define SWDIO_Pin GPIO_PIN_13
#define SWDIO_GPIO_Port GPIOA
#define SWCLK_Pin GPIO_PIN_14
#define SWCLK_GPIO_Port GPIOA
#define JTDI_Pin GPIO_PIN_15
#define JTDI_GPIO_Port GPIOA
#define SWO_Pin GPIO_PIN_3
#define SWO_GPIO_Port GPIOB
/* USER CODE BEGIN Private defines */
/* USER CODE END Private defines */
#ifdef __cplusplus
}
#endif
#endif /* __MAIN_H */

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/* USER CODE BEGIN Header */
/**
**********************************************************************************************************************
* @file stm32h5xx_hal_conf.h
* @author MCD Application Team
* @brief HAL configuration file.
**********************************************************************************************************************
* @attention
*
* Copyright (c) 2023 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
**********************************************************************************************************************
*/
/* USER CODE END Header */
/* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/
#ifndef STM32H5xx_HAL_CONF_H
#define STM32H5xx_HAL_CONF_H
#ifdef __cplusplus
extern "C" {
#endif
/* Exported types ----------------------------------------------------------------------------------------------------*/
/* Exported constants ------------------------------------------------------------------------------------------------*/
/* ########################################### Module Selection ##################################################### */
/**
* @brief This is the list of modules to be used in the HAL driver
*/
#define HAL_MODULE_ENABLED
/*#define HAL_CCB_MODULE_ENABLED */
#define HAL_ADC_MODULE_ENABLED
/*#define HAL_CEC_MODULE_ENABLED */
/*#define HAL_CRC_MODULE_ENABLED */
/*#define HAL_CRYP_MODULE_ENABLED */
#define HAL_DAC_MODULE_ENABLED
/*#define HAL_DCACHE_MODULE_ENABLED */
/*#define HAL_DCMI_MODULE_ENABLED */
/*#define HAL_DTS_MODULE_ENABLED */
#define HAL_FDCAN_MODULE_ENABLED
/*#define HAL_GTZC_MODULE_ENABLED */
/*#define HAL_HASH_MODULE_ENABLED */
/*#define HAL_IWDG_MODULE_ENABLED */
/*#define HAL_I2C_MODULE_ENABLED */
/*#define HAL_I3C_MODULE_ENABLED */
/*#define HAL_I2S_MODULE_ENABLED */
/*#define HAL_LPTIM_MODULE_ENABLED */
/*#define HAL_NAND_MODULE_ENABLED */
/*#define HAL_NOR_MODULE_ENABLED */
/*#define HAL_XSPI_MODULE_ENABLED */
/*#define HAL_OTFDEC_MODULE_ENABLED */
/*#define HAL_PKA_MODULE_ENABLED */
/*#define HAL_RNG_MODULE_ENABLED */
/*#define HAL_RTC_MODULE_ENABLED */
/*#define HAL_SD_MODULE_ENABLED */
/*#define HAL_SDIO_MODULE_ENABLED */
/*#define HAL_MMC_MODULE_ENABLED */
/*#define HAL_SPI_MODULE_ENABLED */
/*#define HAL_SRAM_MODULE_ENABLED */
/*#define HAL_TIM_MODULE_ENABLED */
/*#define HAL_RAMCFG_MODULE_ENABLED */
#define HAL_UART_MODULE_ENABLED
/*#define HAL_USART_MODULE_ENABLED */
/*#define HAL_WWDG_MODULE_ENABLED */
/*#define HAL_PSSI_MODULE_ENABLED */
#define HAL_ICACHE_MODULE_ENABLED
/*#define HAL_PCD_MODULE_ENABLED */
/*#define HAL_HCD_MODULE_ENABLED */
/*#define HAL_SMARTCARD_MODULE_ENABLED */
/*#define HAL_SMBUS_MODULE_ENABLED */
/*#define HAL_IRDA_MODULE_ENABLED */
#define HAL_GPIO_MODULE_ENABLED
#define HAL_EXTI_MODULE_ENABLED
#define HAL_DMA_MODULE_ENABLED
#define HAL_RCC_MODULE_ENABLED
#define HAL_FLASH_MODULE_ENABLED
#define HAL_PWR_MODULE_ENABLED
#define HAL_CORTEX_MODULE_ENABLED
/* ####################################### Oscillator Values adaptation ##############################################*/
/**
* @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
* This value is used by the RCC HAL module to compute the system frequency
* (when HSE is used as system clock source, directly or through the PLL).
*/
#if !defined (HSE_VALUE)
#define HSE_VALUE 25000000U /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */
#if !defined (HSE_STARTUP_TIMEOUT)
#define HSE_STARTUP_TIMEOUT 100U /*!< Time out for HSE start up, in ms */
#endif /* HSE_STARTUP_TIMEOUT */
/**
* @brief Internal Core Speed oscillator (CSI) default value.
* This value is the default CSI range value after Reset.
*/
#if !defined (CSI_VALUE)
#define CSI_VALUE 4000000UL /*!< Value of the Internal oscillator in Hz*/
#endif /* CSI_VALUE */
/**
* @brief Internal High Speed oscillator (HSI) value.
* This value is used by the RCC HAL module to compute the system frequency
* (when HSI is used as system clock source, directly or through the PLL).
*/
#if !defined (HSI_VALUE)
#define HSI_VALUE 64000000UL /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
/**
* @brief Internal High Speed oscillator (HSI48) value for USB FS, SDMMC and RNG.
* This internal oscillator is mainly dedicated to provide a high precision clock to
* the USB peripheral by means of a special Clock Recovery System (CRS) circuitry.
* When the CRS is not used, the HSI48 RC oscillator runs on it default frequency
* which is subject to manufacturing process variations.
*/
#if !defined (HSI48_VALUE)
#define HSI48_VALUE 48000000UL /*!< Value of the Internal High Speed oscillator for USB FS/SDMMC/RNG in Hz.
The real value my vary depending on manufacturing process variations.*/
#endif /* HSI48_VALUE */
/**
* @brief Internal Low Speed oscillator (LSI) value.
*/
#if !defined (LSI_VALUE)
#define LSI_VALUE 32000UL /*!< LSI Typical Value in Hz*/
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
The real value may vary depending on the variations
in voltage and temperature.*/
#if !defined (LSI_STARTUP_TIME)
#define LSI_STARTUP_TIME 130UL /*!< Time out for LSI start up, in us */
#endif /* LSI_STARTUP_TIME */
/**
* @brief External Low Speed oscillator (LSE) value.
* This value is used by the UART, RTC HAL module to compute the system frequency
*/
#if !defined (LSE_VALUE)
#define LSE_VALUE 32768UL /*!< Value of the External oscillator in Hz*/
#endif /* LSE_VALUE */
#if !defined (LSE_STARTUP_TIMEOUT)
#define LSE_STARTUP_TIMEOUT 5000UL /*!< Time out for LSE start up, in ms */
#endif /* LSE_STARTUP_TIMEOUT */
/**
* @brief External clock source for SPI peripheral
* This value is used by the SPI HAL module to compute the SPI clock source
* frequency, this source is inserted directly through I2S_CKIN pad.
*/
#if !defined (EXTERNAL_CLOCK_VALUE)
#define EXTERNAL_CLOCK_VALUE 12288000UL /*!< Value of the External clock in Hz*/
#endif /* EXTERNAL_CLOCK_VALUE */
/* Tip: To avoid modifying this file each time you need to use different HSE,
=== you can define the HSE value in your toolchain compiler preprocessor. */
/* ############################################ System Configuration ################################################ */
/**
* @brief This is the HAL system configuration section
*/
#define VDD_VALUE 3300UL /*!< Value of VDD in mv */
#define TICK_INT_PRIORITY (15UL) /*!< tick interrupt priority (lowest by default) */
#define USE_RTOS 0U
#define PREFETCH_ENABLE 0U /*!< Enable prefetch */
/* ############################################ Assert Selection #################################################### */
/**
* @brief Uncomment the line below to expanse the "assert_param" macro in the
* HAL drivers code
*/
/* #define USE_FULL_ASSERT 1U */
/* ############################################ Register callback feature configuration ############################# */
/**
* @brief Set below the peripheral configuration to "1U" to add the support
* of HAL callback registration/unregistration feature for the HAL
* driver(s). This allows user application to provide specific callback
* functions thanks to HAL_PPP_RegisterCallback() rather than overwriting
* the default weak callback functions (see each stm32h5xx_hal_ppp.h file
* for possible callback identifiers defined in HAL_PPP_CallbackIDTypeDef
* for each PPP peripheral).
*/
#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */
#define USE_HAL_CCB_REGISTER_CALLBACKS 0U /* CCB register callback disabled */
#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */
#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */
#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */
#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */
#define USE_HAL_DTS_REGISTER_CALLBACKS 0U /* DTS register callback disabled */
#define USE_HAL_FDCAN_REGISTER_CALLBACKS 0U /* FDCAN register callback disabled */
#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */
#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */
#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */
#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */
#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */
#define USE_HAL_I3C_REGISTER_CALLBACKS 0U /* I3C register callback disabled */
#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */
#define USE_HAL_IWDG_REGISTER_CALLBACKS 0U /* IWDG register callback disabled */
#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */
#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */
#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */
#define USE_HAL_OTFDEC_REGISTER_CALLBACKS 0U /* OTFDEC register callback disabled */
#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */
#define USE_HAL_PKA_REGISTER_CALLBACKS 0U /* PKA register callback disabled */
#define USE_HAL_RAMCFG_REGISTER_CALLBACKS 0U /* RAMCFG register callback disabled */
#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */
#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */
#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */
#define USE_HAL_SDIO_REGISTER_CALLBACKS 0U /* SDIO register callback disabled */
#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */
#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */
#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */
#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */
#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */
#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */
#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */
#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */
#define USE_HAL_XSPI_REGISTER_CALLBACKS 0U /* XSPI register callback disabled */
/* ############################################ SPI peripheral configuration ######################################## */
/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
* Activated: CRC code is present inside driver
* Deactivated: CRC code cleaned from driver
*/
#define USE_SPI_CRC 0U
/* ################## SDMMC peripheral configuration ######################### */
#define USE_SD_TRANSCEIVER 0U
/* ################## SDIO peripheral configuration ######################### */
#define USE_SDIO_TRANSCEIVER 0U
#define SDIO_MAX_IO_NUMBER 7U
/* Includes ----------------------------------------------------------------------------------------------------------*/
/**
* @brief Include module's header file
*/
#ifdef HAL_RCC_MODULE_ENABLED
#include "stm32h5xx_hal_rcc.h"
#endif /* HAL_RCC_MODULE_ENABLED */
#ifdef HAL_GPIO_MODULE_ENABLED
#include "stm32h5xx_hal_gpio.h"
#endif /* HAL_GPIO_MODULE_ENABLED */
#ifdef HAL_ICACHE_MODULE_ENABLED
#include "stm32h5xx_hal_icache.h"
#endif /* HAL_ICACHE_MODULE_ENABLED */
#ifdef HAL_DCACHE_MODULE_ENABLED
#include "stm32h5xx_hal_dcache.h"
#endif /* HAL_DCACHE_MODULE_ENABLED */
#ifdef HAL_GTZC_MODULE_ENABLED
#include "stm32h5xx_hal_gtzc.h"
#endif /* HAL_GTZC_MODULE_ENABLED */
#ifdef HAL_DMA_MODULE_ENABLED
#include "stm32h5xx_hal_dma.h"
#endif /* HAL_DMA_MODULE_ENABLED */
#ifdef HAL_DTS_MODULE_ENABLED
#include "stm32h5xx_hal_dts.h"
#endif /* HAL_DTS_MODULE_ENABLED */
#ifdef HAL_CORTEX_MODULE_ENABLED
#include "stm32h5xx_hal_cortex.h"
#endif /* HAL_CORTEX_MODULE_ENABLED */
#ifdef HAL_PKA_MODULE_ENABLED
#include "stm32h5xx_hal_pka.h"
#endif /* HAL_PKA_MODULE_ENABLED */
#ifdef HAL_ADC_MODULE_ENABLED
#include "stm32h5xx_hal_adc.h"
#endif /* HAL_ADC_MODULE_ENABLED */
#ifdef HAL_CRC_MODULE_ENABLED
#include "stm32h5xx_hal_crc.h"
#endif /* HAL_CRC_MODULE_ENABLED */
#ifdef HAL_CRYP_MODULE_ENABLED
#include "stm32h5xx_hal_cryp.h"
#endif /* HAL_CRYP_MODULE_ENABLED */
#ifdef HAL_DAC_MODULE_ENABLED
#include "stm32h5xx_hal_dac.h"
#endif /* HAL_DAC_MODULE_ENABLED */
#ifdef HAL_FLASH_MODULE_ENABLED
#include "stm32h5xx_hal_flash.h"
#endif /* HAL_FLASH_MODULE_ENABLED */
#ifdef HAL_HASH_MODULE_ENABLED
#include "stm32h5xx_hal_hash.h"
#endif /* HAL_HASH_MODULE_ENABLED */
#ifdef HAL_SRAM_MODULE_ENABLED
#include "stm32h5xx_hal_sram.h"
#endif /* HAL_SRAM_MODULE_ENABLED */
#ifdef HAL_SDIO_MODULE_ENABLED
#include "stm32h5xx_hal_sdio.h"
#endif /* HAL_SDIO_MODULE_ENABLED */
#ifdef HAL_MMC_MODULE_ENABLED
#include "stm32h5xx_hal_mmc.h"
#endif /* HAL_MMC_MODULE_ENABLED */
#ifdef HAL_NOR_MODULE_ENABLED
#include "stm32h5xx_hal_nor.h"
#endif /* HAL_NOR_MODULE_ENABLED */
#ifdef HAL_NAND_MODULE_ENABLED
#include "stm32h5xx_hal_nand.h"
#endif /* HAL_NAND_MODULE_ENABLED */
#ifdef HAL_I2C_MODULE_ENABLED
#include "stm32h5xx_hal_i2c.h"
#endif /* HAL_I2C_MODULE_ENABLED */
#ifdef HAL_I2S_MODULE_ENABLED
#include "stm32h5xx_hal_i2s.h"
#endif /* HAL_I2S_MODULE_ENABLED */
#ifdef HAL_I3C_MODULE_ENABLED
#include "stm32h5xx_hal_i3c.h"
#endif /* HAL_I3C_MODULE_ENABLED */
#ifdef HAL_IWDG_MODULE_ENABLED
#include "stm32h5xx_hal_iwdg.h"
#endif /* HAL_IWDG_MODULE_ENABLED */
#ifdef HAL_LPTIM_MODULE_ENABLED
#include "stm32h5xx_hal_lptim.h"
#endif /* HAL_LPTIM_MODULE_ENABLED */
#ifdef HAL_PWR_MODULE_ENABLED
#include "stm32h5xx_hal_pwr.h"
#endif /* HAL_PWR_MODULE_ENABLED */
#ifdef HAL_XSPI_MODULE_ENABLED
#include "stm32h5xx_hal_xspi.h"
#endif /* HAL_XSPI_MODULE_ENABLED */
#ifdef HAL_RNG_MODULE_ENABLED
#include "stm32h5xx_hal_rng.h"
#endif /* HAL_RNG_MODULE_ENABLED */
#ifdef HAL_RTC_MODULE_ENABLED
#include "stm32h5xx_hal_rtc.h"
#endif /* HAL_RTC_MODULE_ENABLED */
#ifdef HAL_SD_MODULE_ENABLED
#include "stm32h5xx_hal_sd.h"
#endif /* HAL_SD_MODULE_ENABLED */
#ifdef HAL_SMBUS_MODULE_ENABLED
#include "stm32h5xx_hal_smbus.h"
#endif /* HAL_SMBUS_MODULE_ENABLED */
#ifdef HAL_SPI_MODULE_ENABLED
#include "stm32h5xx_hal_spi.h"
#endif /* HAL_SPI_MODULE_ENABLED */
#ifdef HAL_TIM_MODULE_ENABLED
#include "stm32h5xx_hal_tim.h"
#endif /* HAL_TIM_MODULE_ENABLED */
#ifdef HAL_UART_MODULE_ENABLED
#include "stm32h5xx_hal_uart.h"
#endif /* HAL_UART_MODULE_ENABLED */
#ifdef HAL_USART_MODULE_ENABLED
#include "stm32h5xx_hal_usart.h"
#endif /* HAL_USART_MODULE_ENABLED */
#ifdef HAL_IRDA_MODULE_ENABLED
#include "stm32h5xx_hal_irda.h"
#endif /* HAL_IRDA_MODULE_ENABLED */
#ifdef HAL_SMARTCARD_MODULE_ENABLED
#include "stm32h5xx_hal_smartcard.h"
#endif /* HAL_SMARTCARD_MODULE_ENABLED */
#ifdef HAL_WWDG_MODULE_ENABLED
#include "stm32h5xx_hal_wwdg.h"
#endif /* HAL_WWDG_MODULE_ENABLED */
#ifdef HAL_PCD_MODULE_ENABLED
#include "stm32h5xx_hal_pcd.h"
#endif /* HAL_PCD_MODULE_ENABLED */
#ifdef HAL_CCB_MODULE_ENABLED
#include "stm32h5xx_hal_ccb.h"
#endif /* HAL_CCB_MODULE_ENABLED */
#ifdef HAL_HCD_MODULE_ENABLED
#include "stm32h5xx_hal_hcd.h"
#endif /* HAL_HCD_MODULE_ENABLED */
#ifdef HAL_DCMI_MODULE_ENABLED
#include "stm32h5xx_hal_dcmi.h"
#endif /* HAL_DCMI_MODULE_ENABLED */
#ifdef HAL_EXTI_MODULE_ENABLED
#include "stm32h5xx_hal_exti.h"
#endif /* HAL_EXTI_MODULE_ENABLED */
#ifdef HAL_FDCAN_MODULE_ENABLED
#include "stm32h5xx_hal_fdcan.h"
#endif /* HAL_FDCAN_MODULE_ENABLED */
#ifdef HAL_CEC_MODULE_ENABLED
#include "stm32h5xx_hal_cec.h"
#endif /* HAL_CEC_MODULE_ENABLED */
#ifdef HAL_OTFDEC_MODULE_ENABLED
#include "stm32h5xx_hal_otfdec.h"
#endif /* HAL_OTFDEC_MODULE_ENABLED */
#ifdef HAL_PSSI_MODULE_ENABLED
#include "stm32h5xx_hal_pssi.h"
#endif /* HAL_PSSI_MODULE_ENABLED */
#ifdef HAL_RAMCFG_MODULE_ENABLED
#include "stm32h5xx_hal_ramcfg.h"
#endif /* HAL_RAMCFG_MODULE_ENABLED */
/* Exported macro ----------------------------------------------------------------------------------------------------*/
#ifdef USE_FULL_ASSERT
/**
* @brief The assert_param macro is used for function's parameters check.
* @param expr: If expr is false, it calls assert_failed function
* which reports the name of the source file and the source
* line number of the call that failed.
* If expr is true, it returns no value.
* @retval None
*/
#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
/* Exported functions ----------------------------------------------------------------------------------------------- */
void assert_failed(uint8_t *file, uint32_t line);
#else
#define assert_param(expr) ((void)0U)
#endif /* USE_FULL_ASSERT */
#ifdef __cplusplus
}
#endif
#endif /* STM32H5xx_HAL_CONF_H */

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/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file stm32h5xx_it.h
* @brief This file contains the headers of the interrupt handlers.
******************************************************************************
* @attention
*
* Copyright (c) 2026 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32H5xx_IT_H
#define __STM32H5xx_IT_H
#ifdef __cplusplus
extern "C" {
#endif
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
/* Exported types ------------------------------------------------------------*/
/* USER CODE BEGIN ET */
/* USER CODE END ET */
/* Exported constants --------------------------------------------------------*/
/* USER CODE BEGIN EC */
/* USER CODE END EC */
/* Exported macro ------------------------------------------------------------*/
/* USER CODE BEGIN EM */
/* USER CODE END EM */
/* Exported functions prototypes ---------------------------------------------*/
void NMI_Handler(void);
void HardFault_Handler(void);
void MemManage_Handler(void);
void BusFault_Handler(void);
void UsageFault_Handler(void);
void SVC_Handler(void);
void DebugMon_Handler(void);
void PendSV_Handler(void);
void SysTick_Handler(void);
/* USER CODE BEGIN EFP */
/* USER CODE END EFP */
#ifdef __cplusplus
}
#endif
#endif /* __STM32H5xx_IT_H */

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/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file : main.c
* @brief : Main program body
******************************************************************************
* @attention
*
* Copyright (c) 2026 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Includes ------------------------------------------------------------------*/
#include "main.h"
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
/* Private typedef -----------------------------------------------------------*/
/* USER CODE BEGIN PTD */
/* USER CODE END PTD */
/* Private define ------------------------------------------------------------*/
/* USER CODE BEGIN PD */
/* USER CODE END PD */
/* Private macro -------------------------------------------------------------*/
/* USER CODE BEGIN PM */
/* USER CODE END PM */
/* Private variables ---------------------------------------------------------*/
ADC_HandleTypeDef hadc1;
DAC_HandleTypeDef hdac1;
FDCAN_HandleTypeDef hfdcan1;
UART_HandleTypeDef huart1;
/* USER CODE BEGIN PV */
/* USER CODE END PV */
/* Private function prototypes -----------------------------------------------*/
void SystemClock_Config(void);
static void MPU_Config(void);
static void MX_GPIO_Init(void);
static void MX_ICACHE_Init(void);
static void MX_ADC1_Init(void);
static void MX_DAC1_Init(void);
static void MX_FDCAN1_Init(void);
static void MX_USART1_UART_Init(void);
/* USER CODE BEGIN PFP */
/* USER CODE END PFP */
/* Private user code ---------------------------------------------------------*/
/* USER CODE BEGIN 0 */
/* USER CODE END 0 */
/**
* @brief The application entry point.
* @retval int
*/
int main(void)
{
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* MPU Configuration--------------------------------------------------------*/
MPU_Config();
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
MX_ICACHE_Init();
MX_ADC1_Init();
MX_DAC1_Init();
MX_FDCAN1_Init();
MX_USART1_UART_Init();
/* USER CODE BEGIN 2 */
/* USER CODE END 2 */
/* Infinite loop */
/* USER CODE BEGIN WHILE */
while (1)
{
/* USER CODE END WHILE */
/* USER CODE BEGIN 3 */
}
/* USER CODE END 3 */
}
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
/** Configure the main internal regulator output voltage
*/
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3);
while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_LSI
|RCC_OSCILLATORTYPE_CSI;
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV2;
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
RCC_OscInitStruct.LSIState = RCC_LSI_ON;
RCC_OscInitStruct.CSIState = RCC_CSI_ON;
RCC_OscInitStruct.CSICalibrationValue = RCC_CSICALIBRATION_DEFAULT;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLL1_SOURCE_CSI;
RCC_OscInitStruct.PLL.PLLM = 1;
RCC_OscInitStruct.PLL.PLLN = 129;
RCC_OscInitStruct.PLL.PLLP = 2;
RCC_OscInitStruct.PLL.PLLQ = 6;
RCC_OscInitStruct.PLL.PLLR = 2;
RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1_VCIRANGE_2;
RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1_VCORANGE_WIDE;
RCC_OscInitStruct.PLL.PLLFRACN = 0;
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
{
Error_Handler();
}
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2
|RCC_CLOCKTYPE_PCLK3;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
RCC_ClkInitStruct.APB3CLKDivider = RCC_HCLK_DIV1;
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
{
Error_Handler();
}
/** Configure the programming delay
*/
__HAL_FLASH_SET_PROGRAM_DELAY(FLASH_PROGRAMMING_DELAY_0);
}
/**
* @brief ADC1 Initialization Function
* @param None
* @retval None
*/
static void MX_ADC1_Init(void)
{
/* USER CODE BEGIN ADC1_Init 0 */
/* USER CODE END ADC1_Init 0 */
ADC_ChannelConfTypeDef sConfig = {0};
/* USER CODE BEGIN ADC1_Init 1 */
/* USER CODE END ADC1_Init 1 */
/** Common config
*/
hadc1.Instance = ADC1;
hadc1.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1;
hadc1.Init.Resolution = ADC_RESOLUTION_12B;
hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE;
hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
hadc1.Init.LowPowerAutoWait = DISABLE;
hadc1.Init.ContinuousConvMode = DISABLE;
hadc1.Init.NbrOfConversion = 1;
hadc1.Init.DiscontinuousConvMode = DISABLE;
hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START;
hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
hadc1.Init.DMAContinuousRequests = DISABLE;
hadc1.Init.SamplingMode = ADC_SAMPLING_MODE_NORMAL;
hadc1.Init.Overrun = ADC_OVR_DATA_PRESERVED;
hadc1.Init.OversamplingMode = DISABLE;
if (HAL_ADC_Init(&hadc1) != HAL_OK)
{
Error_Handler();
}
/** Configure Regular Channel
*/
sConfig.Channel = ADC_CHANNEL_TEMPSENSOR;
sConfig.Rank = ADC_REGULAR_RANK_1;
sConfig.SamplingTime = ADC_SAMPLETIME_2CYCLES_5;
sConfig.SingleDiff = ADC_SINGLE_ENDED;
sConfig.OffsetNumber = ADC_OFFSET_NONE;
sConfig.Offset = 0;
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN ADC1_Init 2 */
/* USER CODE END ADC1_Init 2 */
}
/**
* @brief DAC1 Initialization Function
* @param None
* @retval None
*/
static void MX_DAC1_Init(void)
{
/* USER CODE BEGIN DAC1_Init 0 */
/* USER CODE END DAC1_Init 0 */
DAC_ChannelConfTypeDef sConfig = {0};
/* USER CODE BEGIN DAC1_Init 1 */
/* USER CODE END DAC1_Init 1 */
/** DAC Initialization
*/
hdac1.Instance = DAC1;
if (HAL_DAC_Init(&hdac1) != HAL_OK)
{
Error_Handler();
}
/** DAC channel OUT1 config
*/
sConfig.DAC_HighFrequency = DAC_HIGH_FREQUENCY_INTERFACE_MODE_DISABLE;
sConfig.DAC_DMADoubleDataMode = DISABLE;
sConfig.DAC_SignedFormat = DISABLE;
sConfig.DAC_SampleAndHold = DAC_SAMPLEANDHOLD_DISABLE;
sConfig.DAC_Trigger = DAC_TRIGGER_NONE;
sConfig.DAC_ConnectOnChipPeripheral = DAC_CHIPCONNECT_EXTERNAL;
sConfig.DAC_UserTrimming = DAC_TRIMMING_FACTORY;
if (HAL_DAC_ConfigChannel(&hdac1, &sConfig, DAC_CHANNEL_1) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN DAC1_Init 2 */
/* USER CODE END DAC1_Init 2 */
}
/**
* @brief FDCAN1 Initialization Function
* @param None
* @retval None
*/
static void MX_FDCAN1_Init(void)
{
/* USER CODE BEGIN FDCAN1_Init 0 */
/* USER CODE END FDCAN1_Init 0 */
/* USER CODE BEGIN FDCAN1_Init 1 */
/* USER CODE END FDCAN1_Init 1 */
hfdcan1.Instance = FDCAN1;
hfdcan1.Init.ClockDivider = FDCAN_CLOCK_DIV1;
hfdcan1.Init.FrameFormat = FDCAN_FRAME_CLASSIC;
hfdcan1.Init.Mode = FDCAN_MODE_NORMAL;
hfdcan1.Init.AutoRetransmission = DISABLE;
hfdcan1.Init.TransmitPause = DISABLE;
hfdcan1.Init.ProtocolException = DISABLE;
hfdcan1.Init.NominalPrescaler = 16;
hfdcan1.Init.NominalSyncJumpWidth = 1;
hfdcan1.Init.NominalTimeSeg1 = 1;
hfdcan1.Init.NominalTimeSeg2 = 1;
hfdcan1.Init.DataPrescaler = 1;
hfdcan1.Init.DataSyncJumpWidth = 1;
hfdcan1.Init.DataTimeSeg1 = 1;
hfdcan1.Init.DataTimeSeg2 = 1;
hfdcan1.Init.StdFiltersNbr = 0;
hfdcan1.Init.ExtFiltersNbr = 0;
hfdcan1.Init.TxFifoQueueMode = FDCAN_TX_FIFO_OPERATION;
if (HAL_FDCAN_Init(&hfdcan1) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN FDCAN1_Init 2 */
/* USER CODE END FDCAN1_Init 2 */
}
/**
* @brief ICACHE Initialization Function
* @param None
* @retval None
*/
static void MX_ICACHE_Init(void)
{
/* USER CODE BEGIN ICACHE_Init 0 */
/* USER CODE END ICACHE_Init 0 */
/* USER CODE BEGIN ICACHE_Init 1 */
/* USER CODE END ICACHE_Init 1 */
/** Enable instruction cache in 1-way (direct mapped cache)
*/
if (HAL_ICACHE_ConfigAssociativityMode(ICACHE_1WAY) != HAL_OK)
{
Error_Handler();
}
if (HAL_ICACHE_Enable() != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN ICACHE_Init 2 */
/* USER CODE END ICACHE_Init 2 */
}
/**
* @brief USART1 Initialization Function
* @param None
* @retval None
*/
static void MX_USART1_UART_Init(void)
{
/* USER CODE BEGIN USART1_Init 0 */
/* USER CODE END USART1_Init 0 */
/* USER CODE BEGIN USART1_Init 1 */
/* USER CODE END USART1_Init 1 */
huart1.Instance = USART1;
huart1.Init.BaudRate = 115200;
huart1.Init.WordLength = UART_WORDLENGTH_8B;
huart1.Init.StopBits = UART_STOPBITS_1;
huart1.Init.Parity = UART_PARITY_NONE;
huart1.Init.Mode = UART_MODE_TX_RX;
huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
huart1.Init.OverSampling = UART_OVERSAMPLING_16;
huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
huart1.Init.ClockPrescaler = UART_PRESCALER_DIV1;
huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
if (HAL_UART_Init(&huart1) != HAL_OK)
{
Error_Handler();
}
if (HAL_UARTEx_SetTxFifoThreshold(&huart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
{
Error_Handler();
}
if (HAL_UARTEx_SetRxFifoThreshold(&huart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
{
Error_Handler();
}
if (HAL_UARTEx_DisableFifoMode(&huart1) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN USART1_Init 2 */
/* USER CODE END USART1_Init 2 */
}
/**
* @brief GPIO Initialization Function
* @param None
* @retval None
*/
static void MX_GPIO_Init(void)
{
GPIO_InitTypeDef GPIO_InitStruct = {0};
/* USER CODE BEGIN MX_GPIO_Init_1 */
/* USER CODE END MX_GPIO_Init_1 */
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOA_CLK_ENABLE();
__HAL_RCC_GPIOB_CLK_ENABLE();
/*Configure GPIO pins : PA2 PA3 */
GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
GPIO_InitStruct.Alternate = GPIO_AF7_USART2;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
/* USER CODE BEGIN MX_GPIO_Init_2 */
/* USER CODE END MX_GPIO_Init_2 */
}
/* USER CODE BEGIN 4 */
/* USER CODE END 4 */
/* MPU Configuration */
void MPU_Config(void)
{
MPU_Region_InitTypeDef MPU_InitStruct = {0};
MPU_Attributes_InitTypeDef MPU_AttributesInit = {0};
/* Disables the MPU */
HAL_MPU_Disable();
/** Initializes and configures the Region 0 and the memory to be protected
*/
MPU_InitStruct.Enable = MPU_REGION_ENABLE;
MPU_InitStruct.Number = MPU_REGION_NUMBER0;
MPU_InitStruct.BaseAddress = 0x08FFF000;
MPU_InitStruct.LimitAddress = 0x08FFFFFF;
MPU_InitStruct.AttributesIndex = MPU_ATTRIBUTES_NUMBER0;
MPU_InitStruct.AccessPermission = MPU_REGION_ALL_RO;
MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE;
MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE;
HAL_MPU_ConfigRegion(&MPU_InitStruct);
/** Initializes and configures the Attribute 0 and the memory to be protected
*/
MPU_AttributesInit.Number = MPU_ATTRIBUTES_NUMBER0;
MPU_AttributesInit.Attributes = INNER_OUTER(MPU_NOT_CACHEABLE);
HAL_MPU_ConfigMemoryAttributes(&MPU_AttributesInit);
/* Enables the MPU */
HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT);
}
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
__disable_irq();
while (1)
{
}
/* USER CODE END Error_Handler_Debug */
}
#ifdef USE_FULL_ASSERT
/**
* @brief Reports the name of the source file and the source line number
* where the assert_param error has occurred.
* @param file: pointer to the source file name
* @param line: assert_param error line source number
* @retval None
*/
void assert_failed(uint8_t *file, uint32_t line)
{
/* USER CODE BEGIN 6 */
/* User can add his own implementation to report the file name and line number,
ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
/* USER CODE END 6 */
}
#endif /* USE_FULL_ASSERT */

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/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file stm32h5xx_hal_msp.c
* @brief This file provides code for the MSP Initialization
* and de-Initialization codes.
******************************************************************************
* @attention
*
* Copyright (c) 2026 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Includes ------------------------------------------------------------------*/
#include "main.h"
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
/* Private typedef -----------------------------------------------------------*/
/* USER CODE BEGIN TD */
/* USER CODE END TD */
/* Private define ------------------------------------------------------------*/
/* USER CODE BEGIN Define */
/* USER CODE END Define */
/* Private macro -------------------------------------------------------------*/
/* USER CODE BEGIN Macro */
/* USER CODE END Macro */
/* Private variables ---------------------------------------------------------*/
/* USER CODE BEGIN PV */
/* USER CODE END PV */
/* Private function prototypes -----------------------------------------------*/
/* USER CODE BEGIN PFP */
/* USER CODE END PFP */
/* External functions --------------------------------------------------------*/
/* USER CODE BEGIN ExternalFunctions */
/* USER CODE END ExternalFunctions */
/* USER CODE BEGIN 0 */
/* USER CODE END 0 */
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
/* System interrupt init*/
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
/**
* @brief ADC MSP Initialization
* This function configures the hardware resources used in this example
* @param hadc: ADC handle pointer
* @retval None
*/
void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
{
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
if(hadc->Instance==ADC1)
{
/* USER CODE BEGIN ADC1_MspInit 0 */
/* USER CODE END ADC1_MspInit 0 */
/** Initializes the peripherals clock
*/
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADCDAC;
PeriphClkInitStruct.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_HCLK;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
{
Error_Handler();
}
/* Peripheral clock enable */
__HAL_RCC_ADC_CLK_ENABLE();
/* USER CODE BEGIN ADC1_MspInit 1 */
/* USER CODE END ADC1_MspInit 1 */
}
}
/**
* @brief ADC MSP De-Initialization
* This function freeze the hardware resources used in this example
* @param hadc: ADC handle pointer
* @retval None
*/
void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
{
if(hadc->Instance==ADC1)
{
/* USER CODE BEGIN ADC1_MspDeInit 0 */
/* USER CODE END ADC1_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_ADC_CLK_DISABLE();
/* USER CODE BEGIN ADC1_MspDeInit 1 */
/* USER CODE END ADC1_MspDeInit 1 */
}
}
/**
* @brief DAC MSP Initialization
* This function configures the hardware resources used in this example
* @param hdac: DAC handle pointer
* @retval None
*/
void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac)
{
GPIO_InitTypeDef GPIO_InitStruct = {0};
if(hdac->Instance==DAC1)
{
/* USER CODE BEGIN DAC1_MspInit 0 */
/* USER CODE END DAC1_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_DAC1_CLK_ENABLE();
__HAL_RCC_GPIOA_CLK_ENABLE();
/**DAC1 GPIO Configuration
PA4 ------> DAC1_OUT1
*/
GPIO_InitStruct.Pin = GPIO_PIN_4;
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
GPIO_InitStruct.Pull = GPIO_NOPULL;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
/* USER CODE BEGIN DAC1_MspInit 1 */
/* USER CODE END DAC1_MspInit 1 */
}
}
/**
* @brief DAC MSP De-Initialization
* This function freeze the hardware resources used in this example
* @param hdac: DAC handle pointer
* @retval None
*/
void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac)
{
if(hdac->Instance==DAC1)
{
/* USER CODE BEGIN DAC1_MspDeInit 0 */
/* USER CODE END DAC1_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_DAC1_CLK_DISABLE();
/**DAC1 GPIO Configuration
PA4 ------> DAC1_OUT1
*/
HAL_GPIO_DeInit(GPIOA, GPIO_PIN_4);
/* USER CODE BEGIN DAC1_MspDeInit 1 */
/* USER CODE END DAC1_MspDeInit 1 */
}
}
/**
* @brief FDCAN MSP Initialization
* This function configures the hardware resources used in this example
* @param hfdcan: FDCAN handle pointer
* @retval None
*/
void HAL_FDCAN_MspInit(FDCAN_HandleTypeDef* hfdcan)
{
GPIO_InitTypeDef GPIO_InitStruct = {0};
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
if(hfdcan->Instance==FDCAN1)
{
/* USER CODE BEGIN FDCAN1_MspInit 0 */
/* USER CODE END FDCAN1_MspInit 0 */
/** Initializes the peripherals clock
*/
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_FDCAN;
PeriphClkInitStruct.FdcanClockSelection = RCC_FDCANCLKSOURCE_PLL1Q;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
{
Error_Handler();
}
/* Peripheral clock enable */
__HAL_RCC_FDCAN_CLK_ENABLE();
__HAL_RCC_GPIOA_CLK_ENABLE();
/**FDCAN1 GPIO Configuration
PA11 ------> FDCAN1_RX
PA12 ------> FDCAN1_TX
*/
GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
GPIO_InitStruct.Alternate = GPIO_AF9_FDCAN1;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
/* USER CODE BEGIN FDCAN1_MspInit 1 */
/* USER CODE END FDCAN1_MspInit 1 */
}
}
/**
* @brief FDCAN MSP De-Initialization
* This function freeze the hardware resources used in this example
* @param hfdcan: FDCAN handle pointer
* @retval None
*/
void HAL_FDCAN_MspDeInit(FDCAN_HandleTypeDef* hfdcan)
{
if(hfdcan->Instance==FDCAN1)
{
/* USER CODE BEGIN FDCAN1_MspDeInit 0 */
/* USER CODE END FDCAN1_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_FDCAN_CLK_DISABLE();
/**FDCAN1 GPIO Configuration
PA11 ------> FDCAN1_RX
PA12 ------> FDCAN1_TX
*/
HAL_GPIO_DeInit(GPIOA, GPIO_PIN_11|GPIO_PIN_12);
/* USER CODE BEGIN FDCAN1_MspDeInit 1 */
/* USER CODE END FDCAN1_MspDeInit 1 */
}
}
/**
* @brief UART MSP Initialization
* This function configures the hardware resources used in this example
* @param huart: UART handle pointer
* @retval None
*/
void HAL_UART_MspInit(UART_HandleTypeDef* huart)
{
GPIO_InitTypeDef GPIO_InitStruct = {0};
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
if(huart->Instance==USART1)
{
/* USER CODE BEGIN USART1_MspInit 0 */
/* USER CODE END USART1_MspInit 0 */
/** Initializes the peripherals clock
*/
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART1;
PeriphClkInitStruct.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
{
Error_Handler();
}
/* Peripheral clock enable */
__HAL_RCC_USART1_CLK_ENABLE();
__HAL_RCC_GPIOB_CLK_ENABLE();
/**USART1 GPIO Configuration
PB14 ------> USART1_TX
PB15 ------> USART1_RX
*/
GPIO_InitStruct.Pin = GPIO_PIN_14|GPIO_PIN_15;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
GPIO_InitStruct.Alternate = GPIO_AF4_USART1;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
/* USER CODE BEGIN USART1_MspInit 1 */
/* USER CODE END USART1_MspInit 1 */
}
}
/**
* @brief UART MSP De-Initialization
* This function freeze the hardware resources used in this example
* @param huart: UART handle pointer
* @retval None
*/
void HAL_UART_MspDeInit(UART_HandleTypeDef* huart)
{
if(huart->Instance==USART1)
{
/* USER CODE BEGIN USART1_MspDeInit 0 */
/* USER CODE END USART1_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_USART1_CLK_DISABLE();
/**USART1 GPIO Configuration
PB14 ------> USART1_TX
PB15 ------> USART1_RX
*/
HAL_GPIO_DeInit(GPIOB, GPIO_PIN_14|GPIO_PIN_15);
/* USER CODE BEGIN USART1_MspDeInit 1 */
/* USER CODE END USART1_MspDeInit 1 */
}
}
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */

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/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file stm32h5xx_it.c
* @brief Interrupt Service Routines.
******************************************************************************
* @attention
*
* Copyright (c) 2026 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Includes ------------------------------------------------------------------*/
#include "main.h"
#include "stm32h5xx_it.h"
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
/* Private typedef -----------------------------------------------------------*/
/* USER CODE BEGIN TD */
/* USER CODE END TD */
/* Private define ------------------------------------------------------------*/
/* USER CODE BEGIN PD */
/* USER CODE END PD */
/* Private macro -------------------------------------------------------------*/
/* USER CODE BEGIN PM */
/* USER CODE END PM */
/* Private variables ---------------------------------------------------------*/
/* USER CODE BEGIN PV */
/* USER CODE END PV */
/* Private function prototypes -----------------------------------------------*/
/* USER CODE BEGIN PFP */
/* USER CODE END PFP */
/* Private user code ---------------------------------------------------------*/
/* USER CODE BEGIN 0 */
/* USER CODE END 0 */
/* External variables --------------------------------------------------------*/
/* USER CODE BEGIN EV */
/* USER CODE END EV */
/******************************************************************************/
/* Cortex Processor Interruption and Exception Handlers */
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
{
}
/* USER CODE END NonMaskableInt_IRQn 1 */
}
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
{
/* USER CODE BEGIN W1_HardFault_IRQn 0 */
/* USER CODE END W1_HardFault_IRQn 0 */
}
}
/**
* @brief This function handles Memory management fault.
*/
void MemManage_Handler(void)
{
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
{
/* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
/* USER CODE END W1_MemoryManagement_IRQn 0 */
}
}
/**
* @brief This function handles Pre-fetch fault, memory access fault.
*/
void BusFault_Handler(void)
{
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while (1)
{
/* USER CODE BEGIN W1_BusFault_IRQn 0 */
/* USER CODE END W1_BusFault_IRQn 0 */
}
}
/**
* @brief This function handles Undefined instruction or illegal state.
*/
void UsageFault_Handler(void)
{
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while (1)
{
/* USER CODE BEGIN W1_UsageFault_IRQn 0 */
/* USER CODE END W1_UsageFault_IRQn 0 */
}
}
/**
* @brief This function handles System service call via SWI instruction.
*/
void SVC_Handler(void)
{
/* USER CODE BEGIN SVCall_IRQn 0 */
/* USER CODE END SVCall_IRQn 0 */
/* USER CODE BEGIN SVCall_IRQn 1 */
/* USER CODE END SVCall_IRQn 1 */
}
/**
* @brief This function handles Debug monitor.
*/
void DebugMon_Handler(void)
{
/* USER CODE BEGIN DebugMonitor_IRQn 0 */
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
}
/**
* @brief This function handles Pendable request for system service.
*/
void PendSV_Handler(void)
{
/* USER CODE BEGIN PendSV_IRQn 0 */
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
/**
* @brief This function handles System tick timer.
*/
void SysTick_Handler(void)
{
/* USER CODE BEGIN SysTick_IRQn 0 */
/* USER CODE END SysTick_IRQn 0 */
HAL_IncTick();
/* USER CODE BEGIN SysTick_IRQn 1 */
/* USER CODE END SysTick_IRQn 1 */
}
/******************************************************************************/
/* STM32H5xx Peripheral Interrupt Handlers */
/* Add here the Interrupt Handlers for the used peripherals. */
/* For the available peripheral interrupt handler names, */
/* please refer to the startup file (startup_stm32h5xx.s). */
/******************************************************************************/
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */

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/**
******************************************************************************
* @file syscalls.c
* @author Auto-generated by STM32CubeIDE
* @brief STM32CubeIDE Minimal System calls file
*
* For more information about which c-functions
* need which of these lowlevel functions
* please consult the Newlib libc-manual
******************************************************************************
* @attention
*
* Copyright (c) 2020-2026 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Includes */
#include <sys/stat.h>
#include <stdlib.h>
#include <errno.h>
#include <stdio.h>
#include <signal.h>
#include <time.h>
#include <sys/time.h>
#include <sys/times.h>
/* Variables */
extern int __io_putchar(int ch) __attribute__((weak));
extern int __io_getchar(void) __attribute__((weak));
char *__env[1] = { 0 };
char **environ = __env;
/* Functions */
void initialise_monitor_handles()
{
}
int _getpid(void)
{
return 1;
}
int _kill(int pid, int sig)
{
(void)pid;
(void)sig;
errno = EINVAL;
return -1;
}
void _exit (int status)
{
_kill(status, -1);
while (1) {} /* Make sure we hang here */
}
__attribute__((weak)) int _read(int file, char *ptr, int len)
{
(void)file;
int DataIdx;
for (DataIdx = 0; DataIdx < len; DataIdx++)
{
*ptr++ = __io_getchar();
}
return len;
}
__attribute__((weak)) int _write(int file, char *ptr, int len)
{
(void)file;
int DataIdx;
for (DataIdx = 0; DataIdx < len; DataIdx++)
{
__io_putchar(*ptr++);
}
return len;
}
int _close(int file)
{
(void)file;
return -1;
}
int _fstat(int file, struct stat *st)
{
(void)file;
st->st_mode = S_IFCHR;
return 0;
}
int _isatty(int file)
{
(void)file;
return 1;
}
int _lseek(int file, int ptr, int dir)
{
(void)file;
(void)ptr;
(void)dir;
return 0;
}
int _open(char *path, int flags, ...)
{
(void)path;
(void)flags;
/* Pretend like we always fail */
return -1;
}
int _wait(int *status)
{
(void)status;
errno = ECHILD;
return -1;
}
int _unlink(char *name)
{
(void)name;
errno = ENOENT;
return -1;
}
int _times(struct tms *buf)
{
(void)buf;
return -1;
}
int _stat(char *file, struct stat *st)
{
(void)file;
st->st_mode = S_IFCHR;
return 0;
}
int _link(char *old, char *new)
{
(void)old;
(void)new;
errno = EMLINK;
return -1;
}
int _fork(void)
{
errno = EAGAIN;
return -1;
}
int _execve(char *name, char **argv, char **env)
{
(void)name;
(void)argv;
(void)env;
errno = ENOMEM;
return -1;
}

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/**
******************************************************************************
* @file sysmem.c
* @author Generated by STM32CubeIDE
* @brief STM32CubeIDE System Memory calls file
*
* For more information about which C functions
* need which of these lowlevel functions
* please consult the newlib libc manual
******************************************************************************
* @attention
*
* Copyright (c) 2026 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Includes */
#include <errno.h>
#include <stdint.h>
/**
* Pointer to the current high watermark of the heap usage
*/
static uint8_t *__sbrk_heap_end = NULL;
/**
* @brief _sbrk() allocates memory to the newlib heap and is used by malloc
* and others from the C library
*
* @verbatim
* ############################################################################
* # .data # .bss # newlib heap # MSP stack #
* # # # # Reserved by _Min_Stack_Size #
* ############################################################################
* ^-- RAM start ^-- _end _estack, RAM end --^
* @endverbatim
*
* This implementation starts allocating at the '_end' linker symbol
* The '_Min_Stack_Size' linker symbol reserves a memory for the MSP stack
* The implementation considers '_estack' linker symbol to be RAM end
* NOTE: If the MSP stack, at any point during execution, grows larger than the
* reserved size, please increase the '_Min_Stack_Size'.
*
* @param incr Memory size
* @return Pointer to allocated memory
*/
void *_sbrk(ptrdiff_t incr)
{
extern uint8_t _end; /* Symbol defined in the linker script */
extern uint8_t _estack; /* Symbol defined in the linker script */
extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */
const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size;
const uint8_t *max_heap = (uint8_t *)stack_limit;
uint8_t *prev_heap_end;
/* Initialize heap end at first call */
if (NULL == __sbrk_heap_end)
{
__sbrk_heap_end = &_end;
}
/* Protect heap from growing into the reserved MSP stack */
if (__sbrk_heap_end + incr > max_heap)
{
errno = ENOMEM;
return (void *)-1;
}
prev_heap_end = __sbrk_heap_end;
__sbrk_heap_end += incr;
return (void *)prev_heap_end;
}

403
hpsg5-controller-stm32h5/Core/Src/system_stm32h5xx.c Normal file
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/**
******************************************************************************
* @file system_stm32h5xx.c
* @author MCD Application Team
* @brief CMSIS Cortex-M33 Device Peripheral Access Layer System Source File
*
******************************************************************************
* @attention
*
* Copyright (c) 2023 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
* This file provides two functions and one global variable to be called from
* user application:
* - SystemInit(): This function is called at startup just after reset and
* before branch to main program. This call is made inside
* the "startup_stm32h5xx.s" file.
*
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
* by the user application to setup the SysTick
* timer or configure other parameters.
*
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
* be called whenever the core clock is changed
* during program execution.
*
* After each device reset the HSI (64 MHz) is used as system clock source.
* Then SystemInit() function is called, in "startup_stm32h5xx.s" file, to
* configure the system clock before to branch to main program.
*
* This file configures the system clock as follows:
*=============================================================================
*-----------------------------------------------------------------------------
* System Clock source | HSI
*-----------------------------------------------------------------------------
* SYSCLK(Hz) | 64000000
*-----------------------------------------------------------------------------
* HCLK(Hz) | 64000000
*-----------------------------------------------------------------------------
* AHB Prescaler | 1
*-----------------------------------------------------------------------------
* APB1 Prescaler | 1
*-----------------------------------------------------------------------------
* APB2 Prescaler | 1
*-----------------------------------------------------------------------------
* APB3 Prescaler | 1
*-----------------------------------------------------------------------------
* HSI Division factor | 1
*-----------------------------------------------------------------------------
* PLL1_SRC | No clock
*-----------------------------------------------------------------------------
* PLL1_M | Prescaler disabled
*-----------------------------------------------------------------------------
* PLL1_N | 129
*-----------------------------------------------------------------------------
* PLL1_P | 2
*-----------------------------------------------------------------------------
* PLL1_Q | 2
*-----------------------------------------------------------------------------
* PLL1_R | 2
*-----------------------------------------------------------------------------
* PLL1_FRACN | 0
*-----------------------------------------------------------------------------
* PLL2_SRC | No clock
*-----------------------------------------------------------------------------
* PLL2_M | Prescaler disabled
*-----------------------------------------------------------------------------
* PLL2_N | 129
*-----------------------------------------------------------------------------
* PLL2_P | 2
*-----------------------------------------------------------------------------
* PLL2_Q | 2
*-----------------------------------------------------------------------------
* PLL2_R | 2
*-----------------------------------------------------------------------------
* PLL2_FRACN | 0
*-----------------------------------------------------------------------------
* PLL3_SRC | No clock
*-----------------------------------------------------------------------------
* PLL3_M | Prescaler disabled
*-----------------------------------------------------------------------------
* PLL3_N | 129
*-----------------------------------------------------------------------------
* PLL3_P | 2
*-----------------------------------------------------------------------------
* PLL3_Q | 2
*-----------------------------------------------------------------------------
* PLL3_R | 2
*-----------------------------------------------------------------------------
* PLL3_FRACN | 0
*-----------------------------------------------------------------------------
*=============================================================================
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup STM32H5xx_system
* @{
*/
/** @addtogroup STM32H5xx_System_Private_Includes
* @{
*/
#include "stm32h5xx.h"
/**
* @}
*/
/** @addtogroup STM32H5xx_System_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @addtogroup STM32H5xx_System_Private_Defines
* @{
*/
#if !defined (HSE_VALUE)
#define HSE_VALUE (25000000UL) /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */
#if !defined (CSI_VALUE)
#define CSI_VALUE (4000000UL) /*!< Value of the Internal oscillator in Hz*/
#endif /* CSI_VALUE */
#if !defined (HSI_VALUE)
#define HSI_VALUE (64000000UL) /*!< Value of the Internal oscillator in Hz */
#endif /* HSI_VALUE */
/************************* Miscellaneous Configuration ************************/
/*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */
/* #define VECT_TAB_SRAM */
#if !defined(VECT_TAB_OFFSET)
#define VECT_TAB_OFFSET 0x00U /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
#endif /* VECT_TAB_OFFSET */
/******************************************************************************/
/**
* @}
*/
/** @addtogroup STM32H5xx_System_Private_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup STM32H5xx_System_Private_Variables
* @{
*/
/* The SystemCoreClock variable is updated in three ways:
1) by calling CMSIS function SystemCoreClockUpdate()
2) by calling HAL API function HAL_RCC_GetHCLKFreq()
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
Note: If you use this function to configure the system clock; then there
is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically.
*/
uint32_t SystemCoreClock = 64000000U;
const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
/**
* @}
*/
/** @addtogroup STM32H5xx_System_Private_FunctionPrototypes
* @{
*/
/**
* @}
*/
/** @addtogroup STM32H5xx_System_Private_Functions
* @{
*/
/**
* @brief Setup the microcontroller system.
* @param None
* @retval None
*/
void SystemInit(void)
{
uint32_t reg_opsr;
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 20U)|(3UL << 22U)); /* set CP10 and CP11 Full Access */
#endif
/* Reset the RCC clock configuration to the default reset state ------------*/
/* Set HSION bit while preserving the current HSIDIV value*/
RCC->CR = (RCC->CR & RCC_CR_HSIDIV_Msk) | RCC_CR_HSION;
/* Reset CFGR register */
RCC->CFGR1 = 0U;
RCC->CFGR2 = 0U;
/* Reset HSEON, HSECSSON, HSEBYP, HSEEXT, HSIDIV, HSIKERON, CSION, CSIKERON, HSI48 and PLLxON bits */
#if defined(RCC_CR_PLL3ON)
RCC->CR &= ~(RCC_CR_HSEON | RCC_CR_HSECSSON | RCC_CR_HSEBYP | RCC_CR_HSEEXT | RCC_CR_HSIKERON | \
RCC_CR_CSION | RCC_CR_CSIKERON |RCC_CR_HSI48ON | RCC_CR_PLL1ON | RCC_CR_PLL2ON | RCC_CR_PLL3ON);
#else
RCC->CR &= ~(RCC_CR_HSEON | RCC_CR_HSECSSON | RCC_CR_HSEBYP | RCC_CR_HSEEXT | RCC_CR_HSIKERON | \
RCC_CR_CSION | RCC_CR_CSIKERON |RCC_CR_HSI48ON | RCC_CR_PLL1ON | RCC_CR_PLL2ON);
#endif
/* Reset PLLxCFGR register */
RCC->PLL1CFGR = 0U;
RCC->PLL2CFGR = 0U;
#if defined(RCC_CR_PLL3ON)
RCC->PLL3CFGR = 0U;
#endif /* RCC_CR_PLL3ON */
/* Reset PLL1DIVR register */
RCC->PLL1DIVR = 0x01010280U;
/* Reset PLL1FRACR register */
RCC->PLL1FRACR = 0x00000000U;
/* Reset PLL2DIVR register */
RCC->PLL2DIVR = 0x01010280U;
/* Reset PLL2FRACR register */
RCC->PLL2FRACR = 0x00000000U;
#if defined(RCC_CR_PLL3ON)
/* Reset PLL3DIVR register */
RCC->PLL3DIVR = 0x01010280U;
/* Reset PLL3FRACR register */
RCC->PLL3FRACR = 0x00000000U;
#endif /* RCC_CR_PLL3ON */
/* Reset HSEBYP bit */
RCC->CR &= ~(RCC_CR_HSEBYP);
/* Disable all interrupts */
RCC->CIER = 0U;
/* Configure the Vector Table location add offset address ------------------*/
#ifdef VECT_TAB_SRAM
SCB->VTOR = SRAM1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#else
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
#endif /* VECT_TAB_SRAM */
/* Check OPSR register to verify if there is an ongoing swap or option bytes update interrupted by a reset */
reg_opsr = FLASH->OPSR & FLASH_OPSR_CODE_OP;
if ((reg_opsr == FLASH_OPSR_CODE_OP) || (reg_opsr == (FLASH_OPSR_CODE_OP_2 | FLASH_OPSR_CODE_OP_1)))
{
/* Check FLASH Option Control Register access */
if ((FLASH->OPTCR & FLASH_OPTCR_OPTLOCK) != 0U)
{
/* Authorizes the Option Byte registers programming */
FLASH->OPTKEYR = 0x08192A3BU;
FLASH->OPTKEYR = 0x4C5D6E7FU;
}
/* Launch the option bytes change operation */
FLASH->OPTCR |= FLASH_OPTCR_OPTSTART;
/* Lock the FLASH Option Control Register access */
FLASH->OPTCR |= FLASH_OPTCR_OPTLOCK;
}
}
/**
* @brief Update SystemCoreClock variable according to Clock Register Values.
* The SystemCoreClock variable contains the core clock (HCLK), it can
* be used by the user application to setup the SysTick timer or configure
* other parameters.
*
* @note Each time the core clock (HCLK) changes, this function must be called
* to update SystemCoreClock variable value. Otherwise, any configuration
* based on this variable will be incorrect.
*
* @note - The system frequency computed by this function is not the real
* frequency in the chip. It is calculated based on the predefined
* constant and the selected clock source:
*
* - If SYSCLK source is CSI, SystemCoreClock will contain the CSI_VALUE(*)
*
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
*
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
*
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
* or HSI_VALUE(**) or CSI_VALUE(*) multiplied/divided by the PLL factors.
*
* (*) CSI_VALUE is a constant defined in stm32h5xx_hal.h file (default value
* 4 MHz) but the real value may vary depending on the variations
* in voltage and temperature.
*
* (**) HSI_VALUE is a constant defined in stm32h5xx_hal.h file (default value
* 64 MHz) but the real value may vary depending on the variations
* in voltage and temperature.
*
* (***) HSE_VALUE is a constant defined in stm32h5xx_hal.h file (default value
* 25 MHz), user has to ensure that HSE_VALUE is same as the real
* frequency of the crystal used. Otherwise, this function may
* have wrong result.
*
* - The result of this function could be not correct when using fractional
* value for HSE crystal.
*
* @param None
* @retval None
*/
void SystemCoreClockUpdate(void)
{
uint32_t pllp, pllsource, pllm, pllfracen, hsivalue, tmp;
float_t fracn1, pllvco;
/* Get SYSCLK source -------------------------------------------------------*/
switch (RCC->CFGR1 & RCC_CFGR1_SWS)
{
case 0x00UL: /* HSI used as system clock source */
SystemCoreClock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3));
break;
case 0x08UL: /* CSI used as system clock source */
SystemCoreClock = CSI_VALUE;
break;
case 0x10UL: /* HSE used as system clock source */
SystemCoreClock = HSE_VALUE;
break;
case 0x18UL: /* PLL1 used as system clock source */
/* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN
SYSCLK = PLL_VCO / PLLR
*/
pllsource = (RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1SRC);
pllm = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1M)>> RCC_PLL1CFGR_PLL1M_Pos);
pllfracen = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1FRACEN)>>RCC_PLL1CFGR_PLL1FRACEN_Pos);
fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_PLL1FRACN)>> RCC_PLL1FRACR_PLL1FRACN_Pos));
switch (pllsource)
{
case 0x01UL: /* HSI used as PLL clock source */
hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ;
pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + \
(fracn1/(float_t)0x2000) +(float_t)1 );
break;
case 0x02UL: /* CSI used as PLL clock source */
pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + \
(fracn1/(float_t)0x2000) +(float_t)1 );
break;
case 0x03UL: /* HSE used as PLL clock source */
pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + \
(fracn1/(float_t)0x2000) +(float_t)1 );
break;
default: /* No clock sent to PLL*/
pllvco = (float_t) 0U;
break;
}
pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1P) >>RCC_PLL1DIVR_PLL1P_Pos) + 1U ) ;
SystemCoreClock = (uint32_t)(float_t)(pllvco/(float_t)pllp);
break;
default:
SystemCoreClock = HSI_VALUE;
break;
}
/* Compute HCLK clock frequency --------------------------------------------*/
/* Get HCLK prescaler */
tmp = AHBPrescTable[((RCC->CFGR2 & RCC_CFGR2_HPRE) >> RCC_CFGR2_HPRE_Pos)];
/* HCLK clock frequency */
SystemCoreClock >>= tmp;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/

647
hpsg5-controller-stm32h5/Core/Startup/startup_stm32h533retx.s Normal file
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@@ -0,0 +1,647 @@
/**
******************************************************************************
* @file startup_stm32h533xx.s
* @author MCD Application Team
* @brief STM32h533xx devices vector table GCC toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address,
* - Configure the clock system
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M33 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* Copyright (c) 2023 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m33
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
.equ BootRAM, 0xF1E0F85F
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* set stack pointer */
ldr r0, =_sstack
msr MSPLIM, r0 /* set stack pointer limit */
/* Call the clock system initialization function.*/
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
ldr r2, =_sidata
movs r3, #0
b LoopCopyDataInit
CopyDataInit:
ldr r4, [r2, r3]
str r4, [r0, r3]
adds r3, r3, #4
LoopCopyDataInit:
adds r4, r0, r3
cmp r4, r1
bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
movs r3, #0
b LoopFillZerobss
FillZerobss:
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
cmp r2, r4
bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
LoopForever:
b LoopForever
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The STM32h533xx vector table. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word SecureFault_Handler
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler
.word PVD_AVD_IRQHandler
.word RTC_IRQHandler
.word RTC_S_IRQHandler
.word TAMP_IRQHandler
.word RAMCFG_IRQHandler
.word FLASH_IRQHandler
.word FLASH_S_IRQHandler
.word GTZC_IRQHandler
.word RCC_IRQHandler
.word RCC_S_IRQHandler
.word EXTI0_IRQHandler
.word EXTI1_IRQHandler
.word EXTI2_IRQHandler
.word EXTI3_IRQHandler
.word EXTI4_IRQHandler
.word EXTI5_IRQHandler
.word EXTI6_IRQHandler
.word EXTI7_IRQHandler
.word EXTI8_IRQHandler
.word EXTI9_IRQHandler
.word EXTI10_IRQHandler
.word EXTI11_IRQHandler
.word EXTI12_IRQHandler
.word EXTI13_IRQHandler
.word EXTI14_IRQHandler
.word EXTI15_IRQHandler
.word GPDMA1_Channel0_IRQHandler
.word GPDMA1_Channel1_IRQHandler
.word GPDMA1_Channel2_IRQHandler
.word GPDMA1_Channel3_IRQHandler
.word GPDMA1_Channel4_IRQHandler
.word GPDMA1_Channel5_IRQHandler
.word GPDMA1_Channel6_IRQHandler
.word GPDMA1_Channel7_IRQHandler
.word IWDG_IRQHandler
.word SAES_IRQHandler
.word ADC1_IRQHandler
.word DAC1_IRQHandler
.word FDCAN1_IT0_IRQHandler
.word FDCAN1_IT1_IRQHandler
.word TIM1_BRK_IRQHandler
.word TIM1_UP_IRQHandler
.word TIM1_TRG_COM_IRQHandler
.word TIM1_CC_IRQHandler
.word TIM2_IRQHandler
.word TIM3_IRQHandler
.word TIM4_IRQHandler
.word TIM5_IRQHandler
.word TIM6_IRQHandler
.word TIM7_IRQHandler
.word I2C1_EV_IRQHandler
.word I2C1_ER_IRQHandler
.word I2C2_EV_IRQHandler
.word I2C2_ER_IRQHandler
.word SPI1_IRQHandler
.word SPI2_IRQHandler
.word SPI3_IRQHandler
.word USART1_IRQHandler
.word USART2_IRQHandler
.word USART3_IRQHandler
.word UART4_IRQHandler
.word UART5_IRQHandler
.word LPUART1_IRQHandler
.word LPTIM1_IRQHandler
.word TIM8_BRK_IRQHandler
.word TIM8_UP_IRQHandler
.word TIM8_TRG_COM_IRQHandler
.word TIM8_CC_IRQHandler
.word ADC2_IRQHandler
.word LPTIM2_IRQHandler
.word TIM15_IRQHandler
.word 0
.word 0
.word USB_DRD_FS_IRQHandler
.word CRS_IRQHandler
.word UCPD1_IRQHandler
.word FMC_IRQHandler
.word OCTOSPI1_IRQHandler
.word SDMMC1_IRQHandler
.word I2C3_EV_IRQHandler
.word I2C3_ER_IRQHandler
.word SPI4_IRQHandler
.word 0
.word 0
.word USART6_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word GPDMA2_Channel0_IRQHandler
.word GPDMA2_Channel1_IRQHandler
.word GPDMA2_Channel2_IRQHandler
.word GPDMA2_Channel3_IRQHandler
.word GPDMA2_Channel4_IRQHandler
.word GPDMA2_Channel5_IRQHandler
.word GPDMA2_Channel6_IRQHandler
.word GPDMA2_Channel7_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word 0
.word FPU_IRQHandler
.word ICACHE_IRQHandler
.word DCACHE1_IRQHandler
.word 0
.word 0
.word DCMI_PSSI_IRQHandler
.word FDCAN2_IT0_IRQHandler
.word FDCAN2_IT1_IRQHandler
.word 0
.word 0
.word DTS_IRQHandler
.word RNG_IRQHandler
.word OTFDEC1_IRQHandler
.word AES_IRQHandler
.word HASH_IRQHandler
.word PKA_IRQHandler
.word CEC_IRQHandler
.word TIM12_IRQHandler
.word 0
.word 0
.word I3C1_EV_IRQHandler
.word I3C1_ER_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word I3C2_EV_IRQHandler
.word I3C2_ER_IRQHandler
.size g_pfnVectors, .-g_pfnVectors
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SecureFault_Handler
.thumb_set SecureFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_AVD_IRQHandler
.thumb_set PVD_AVD_IRQHandler,Default_Handler
.weak RTC_IRQHandler
.thumb_set RTC_IRQHandler,Default_Handler
.weak RTC_S_IRQHandler
.thumb_set RTC_S_IRQHandler,Default_Handler
.weak TAMP_IRQHandler
.thumb_set TAMP_IRQHandler,Default_Handler
.weak RAMCFG_IRQHandler
.thumb_set RAMCFG_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak FLASH_S_IRQHandler
.thumb_set FLASH_S_IRQHandler,Default_Handler
.weak GTZC_IRQHandler
.thumb_set GTZC_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak RCC_S_IRQHandler
.thumb_set RCC_S_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak EXTI5_IRQHandler
.thumb_set EXTI5_IRQHandler,Default_Handler
.weak EXTI6_IRQHandler
.thumb_set EXTI6_IRQHandler,Default_Handler
.weak EXTI7_IRQHandler
.thumb_set EXTI7_IRQHandler,Default_Handler
.weak EXTI8_IRQHandler
.thumb_set EXTI8_IRQHandler,Default_Handler
.weak EXTI9_IRQHandler
.thumb_set EXTI9_IRQHandler,Default_Handler
.weak EXTI10_IRQHandler
.thumb_set EXTI10_IRQHandler,Default_Handler
.weak EXTI11_IRQHandler
.thumb_set EXTI11_IRQHandler,Default_Handler
.weak EXTI12_IRQHandler
.thumb_set EXTI12_IRQHandler,Default_Handler
.weak EXTI13_IRQHandler
.thumb_set EXTI13_IRQHandler,Default_Handler
.weak EXTI14_IRQHandler
.thumb_set EXTI14_IRQHandler,Default_Handler
.weak EXTI15_IRQHandler
.thumb_set EXTI15_IRQHandler,Default_Handler
.weak GPDMA1_Channel0_IRQHandler
.thumb_set GPDMA1_Channel0_IRQHandler,Default_Handler
.weak GPDMA1_Channel1_IRQHandler
.thumb_set GPDMA1_Channel1_IRQHandler,Default_Handler
.weak GPDMA1_Channel2_IRQHandler
.thumb_set GPDMA1_Channel2_IRQHandler,Default_Handler
.weak GPDMA1_Channel3_IRQHandler
.thumb_set GPDMA1_Channel3_IRQHandler,Default_Handler
.weak GPDMA1_Channel4_IRQHandler
.thumb_set GPDMA1_Channel4_IRQHandler,Default_Handler
.weak GPDMA1_Channel5_IRQHandler
.thumb_set GPDMA1_Channel5_IRQHandler,Default_Handler
.weak GPDMA1_Channel6_IRQHandler
.thumb_set GPDMA1_Channel6_IRQHandler,Default_Handler
.weak GPDMA1_Channel7_IRQHandler
.thumb_set GPDMA1_Channel7_IRQHandler,Default_Handler
.weak IWDG_IRQHandler
.thumb_set IWDG_IRQHandler,Default_Handler
.weak SAES_IRQHandler
.thumb_set SAES_IRQHandler,Default_Handler
.weak ADC1_IRQHandler
.thumb_set ADC1_IRQHandler,Default_Handler
.weak DAC1_IRQHandler
.thumb_set DAC1_IRQHandler,Default_Handler
.weak FDCAN1_IT0_IRQHandler
.thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
.weak FDCAN1_IT1_IRQHandler
.thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
.weak TIM1_BRK_IRQHandler
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
.weak TIM1_UP_IRQHandler
.thumb_set TIM1_UP_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_IRQHandler
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak TIM5_IRQHandler
.thumb_set TIM5_IRQHandler,Default_Handler
.weak TIM6_IRQHandler
.thumb_set TIM6_IRQHandler,Default_Handler
.weak TIM7_IRQHandler
.thumb_set TIM7_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak UART4_IRQHandler
.thumb_set UART4_IRQHandler,Default_Handler
.weak UART5_IRQHandler
.thumb_set UART5_IRQHandler,Default_Handler
.weak LPUART1_IRQHandler
.thumb_set LPUART1_IRQHandler,Default_Handler
.weak LPTIM1_IRQHandler
.thumb_set LPTIM1_IRQHandler,Default_Handler
.weak TIM8_BRK_IRQHandler
.thumb_set TIM8_BRK_IRQHandler,Default_Handler
.weak TIM8_UP_IRQHandler
.thumb_set TIM8_UP_IRQHandler,Default_Handler
.weak TIM8_TRG_COM_IRQHandler
.thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
.weak TIM8_CC_IRQHandler
.thumb_set TIM8_CC_IRQHandler,Default_Handler
.weak ADC2_IRQHandler
.thumb_set ADC2_IRQHandler,Default_Handler
.weak LPTIM2_IRQHandler
.thumb_set LPTIM2_IRQHandler,Default_Handler
.weak TIM15_IRQHandler
.thumb_set TIM15_IRQHandler,Default_Handler
.weak USB_DRD_FS_IRQHandler
.thumb_set USB_DRD_FS_IRQHandler,Default_Handler
.weak CRS_IRQHandler
.thumb_set CRS_IRQHandler,Default_Handler
.weak UCPD1_IRQHandler
.thumb_set UCPD1_IRQHandler,Default_Handler
.weak FMC_IRQHandler
.thumb_set FMC_IRQHandler,Default_Handler
.weak OCTOSPI1_IRQHandler
.thumb_set OCTOSPI1_IRQHandler,Default_Handler
.weak SDMMC1_IRQHandler
.thumb_set SDMMC1_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak SPI4_IRQHandler
.thumb_set SPI4_IRQHandler,Default_Handler
.weak USART6_IRQHandler
.thumb_set USART6_IRQHandler,Default_Handler
.weak GPDMA2_Channel0_IRQHandler
.thumb_set GPDMA2_Channel0_IRQHandler,Default_Handler
.weak GPDMA2_Channel1_IRQHandler
.thumb_set GPDMA2_Channel1_IRQHandler,Default_Handler
.weak GPDMA2_Channel2_IRQHandler
.thumb_set GPDMA2_Channel2_IRQHandler,Default_Handler
.weak GPDMA2_Channel3_IRQHandler
.thumb_set GPDMA2_Channel3_IRQHandler,Default_Handler
.weak GPDMA2_Channel4_IRQHandler
.thumb_set GPDMA2_Channel4_IRQHandler,Default_Handler
.weak GPDMA2_Channel5_IRQHandler
.thumb_set GPDMA2_Channel5_IRQHandler,Default_Handler
.weak GPDMA2_Channel6_IRQHandler
.thumb_set GPDMA2_Channel6_IRQHandler,Default_Handler
.weak GPDMA2_Channel7_IRQHandler
.thumb_set GPDMA2_Channel7_IRQHandler,Default_Handler
.weak FPU_IRQHandler
.thumb_set FPU_IRQHandler,Default_Handler
.weak ICACHE_IRQHandler
.thumb_set ICACHE_IRQHandler,Default_Handler
.weak DCACHE1_IRQHandler
.thumb_set DCACHE1_IRQHandler,Default_Handler
.weak DCMI_PSSI_IRQHandler
.thumb_set DCMI_PSSI_IRQHandler,Default_Handler
.weak FDCAN2_IT0_IRQHandler
.thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
.weak FDCAN2_IT1_IRQHandler
.thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
.weak DTS_IRQHandler
.thumb_set DTS_IRQHandler,Default_Handler
.weak RNG_IRQHandler
.thumb_set RNG_IRQHandler,Default_Handler
.weak OTFDEC1_IRQHandler
.thumb_set OTFDEC1_IRQHandler,Default_Handler
.weak AES_IRQHandler
.thumb_set AES_IRQHandler,Default_Handler
.weak HASH_IRQHandler
.thumb_set HASH_IRQHandler,Default_Handler
.weak PKA_IRQHandler
.thumb_set PKA_IRQHandler,Default_Handler
.weak CEC_IRQHandler
.thumb_set CEC_IRQHandler,Default_Handler
.weak TIM12_IRQHandler
.thumb_set TIM12_IRQHandler,Default_Handler
.weak I3C1_EV_IRQHandler
.thumb_set I3C1_EV_IRQHandler,Default_Handler
.weak I3C1_ER_IRQHandler
.thumb_set I3C1_ER_IRQHandler,Default_Handler
.weak I3C2_EV_IRQHandler
.thumb_set I3C2_EV_IRQHandler,Default_Handler
.weak I3C2_ER_IRQHandler
.thumb_set I3C2_ER_IRQHandler,Default_Handler

10
hpsg5-controller-stm32h5/Debug/Core/Src/main.cyclo Normal file
View File

@@ -0,0 +1,10 @@
../Core/Src/main.c:77:5:main 1
../Core/Src/main.c:129:6:SystemClock_Config 4
../Core/Src/main.c:192:13:MX_ADC1_Init 3
../Core/Src/main.c:251:13:MX_DAC1_Init 3
../Core/Src/main.c:296:13:MX_FDCAN1_Init 2
../Core/Src/main.c:339:13:MX_ICACHE_Init 3
../Core/Src/main.c:371:13:MX_USART1_UART_Init 5
../Core/Src/main.c:419:13:MX_GPIO_Init 1
../Core/Src/main.c:449:6:MPU_Config 1
../Core/Src/main.c:485:6:Error_Handler 1

68
hpsg5-controller-stm32h5/Debug/Core/Src/main.d Normal file
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@@ -0,0 +1,68 @@
Core/Src/main.o: ../Core/Src/main.c ../Core/Inc/main.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal.h \
../Core/Inc/stm32h5xx_hal_conf.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rcc.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_def.h \
../Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h5xx.h \
../Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h533xx.h \
../Drivers/CMSIS/Include/core_cm33.h \
../Drivers/CMSIS/Include/cmsis_version.h \
../Drivers/CMSIS/Include/cmsis_compiler.h \
../Drivers/CMSIS/Include/cmsis_gcc.h \
../Drivers/CMSIS/Include/mpu_armv8.h \
../Drivers/CMSIS/Device/ST/STM32H5xx/Include/system_stm32h5xx.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rcc_ex.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_gpio.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_gpio_ex.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_icache.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_dma.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_dma_ex.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_cortex.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_adc.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_adc.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_adc_ex.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_dac.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_dac_ex.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_flash.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_flash_ex.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pwr.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pwr_ex.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_uart.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_uart_ex.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_exti.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_fdcan.h
../Core/Inc/main.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal.h:
../Core/Inc/stm32h5xx_hal_conf.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rcc.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_def.h:
../Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h5xx.h:
../Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h533xx.h:
../Drivers/CMSIS/Include/core_cm33.h:
../Drivers/CMSIS/Include/cmsis_version.h:
../Drivers/CMSIS/Include/cmsis_compiler.h:
../Drivers/CMSIS/Include/cmsis_gcc.h:
../Drivers/CMSIS/Include/mpu_armv8.h:
../Drivers/CMSIS/Device/ST/STM32H5xx/Include/system_stm32h5xx.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rcc_ex.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_gpio.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_gpio_ex.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_icache.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_dma.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_dma_ex.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_cortex.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_adc.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_adc.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_adc_ex.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_dac.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_dac_ex.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_flash.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_flash_ex.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pwr.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pwr_ex.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_uart.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_uart_ex.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_exti.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_fdcan.h:

BIN
hpsg5-controller-stm32h5/Debug/Core/Src/main.o Normal file
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10
hpsg5-controller-stm32h5/Debug/Core/Src/main.su Normal file
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@@ -0,0 +1,10 @@
../Core/Src/main.c:77:5:main 8 static
../Core/Src/main.c:129:6:SystemClock_Config 120 static
../Core/Src/main.c:192:13:MX_ADC1_Init 40 static
../Core/Src/main.c:251:13:MX_DAC1_Init 56 static
../Core/Src/main.c:296:13:MX_FDCAN1_Init 8 static
../Core/Src/main.c:339:13:MX_ICACHE_Init 8 static
../Core/Src/main.c:371:13:MX_USART1_UART_Init 8 static
../Core/Src/main.c:419:13:MX_GPIO_Init 40 static
../Core/Src/main.c:449:6:MPU_Config 32 static
../Core/Src/main.c:485:6:Error_Handler 4 static,ignoring_inline_asm

9
hpsg5-controller-stm32h5/Debug/Core/Src/stm32h5xx_hal_msp.cyclo Normal file
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@@ -0,0 +1,9 @@
../Core/Src/stm32h5xx_hal_msp.c:62:6:HAL_MspInit 1
../Core/Src/stm32h5xx_hal_msp.c:82:6:HAL_ADC_MspInit 3
../Core/Src/stm32h5xx_hal_msp.c:116:6:HAL_ADC_MspDeInit 2
../Core/Src/stm32h5xx_hal_msp.c:138:6:HAL_DAC_MspInit 2
../Core/Src/stm32h5xx_hal_msp.c:172:6:HAL_DAC_MspDeInit 2
../Core/Src/stm32h5xx_hal_msp.c:200:6:HAL_FDCAN_MspInit 3
../Core/Src/stm32h5xx_hal_msp.c:248:6:HAL_FDCAN_MspDeInit 2
../Core/Src/stm32h5xx_hal_msp.c:277:6:HAL_UART_MspInit 3
../Core/Src/stm32h5xx_hal_msp.c:325:6:HAL_UART_MspDeInit 2

68
hpsg5-controller-stm32h5/Debug/Core/Src/stm32h5xx_hal_msp.d Normal file
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@@ -0,0 +1,68 @@
Core/Src/stm32h5xx_hal_msp.o: ../Core/Src/stm32h5xx_hal_msp.c \
../Core/Inc/main.h ../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal.h \
../Core/Inc/stm32h5xx_hal_conf.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rcc.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_def.h \
../Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h5xx.h \
../Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h533xx.h \
../Drivers/CMSIS/Include/core_cm33.h \
../Drivers/CMSIS/Include/cmsis_version.h \
../Drivers/CMSIS/Include/cmsis_compiler.h \
../Drivers/CMSIS/Include/cmsis_gcc.h \
../Drivers/CMSIS/Include/mpu_armv8.h \
../Drivers/CMSIS/Device/ST/STM32H5xx/Include/system_stm32h5xx.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rcc_ex.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_gpio.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_gpio_ex.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_icache.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_dma.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_dma_ex.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_cortex.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_adc.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_adc.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_adc_ex.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_dac.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_dac_ex.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_flash.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_flash_ex.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pwr.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pwr_ex.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_uart.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_uart_ex.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_exti.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_fdcan.h
../Core/Inc/main.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal.h:
../Core/Inc/stm32h5xx_hal_conf.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rcc.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_def.h:
../Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h5xx.h:
../Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h533xx.h:
../Drivers/CMSIS/Include/core_cm33.h:
../Drivers/CMSIS/Include/cmsis_version.h:
../Drivers/CMSIS/Include/cmsis_compiler.h:
../Drivers/CMSIS/Include/cmsis_gcc.h:
../Drivers/CMSIS/Include/mpu_armv8.h:
../Drivers/CMSIS/Device/ST/STM32H5xx/Include/system_stm32h5xx.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rcc_ex.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_gpio.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_gpio_ex.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_icache.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_dma.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_dma_ex.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_cortex.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_adc.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_adc.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_adc_ex.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_dac.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_dac_ex.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_flash.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_flash_ex.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pwr.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pwr_ex.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_uart.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_uart_ex.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_exti.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_fdcan.h:

BIN
hpsg5-controller-stm32h5/Debug/Core/Src/stm32h5xx_hal_msp.o Normal file
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9
hpsg5-controller-stm32h5/Debug/Core/Src/stm32h5xx_hal_msp.su Normal file
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@@ -0,0 +1,9 @@
../Core/Src/stm32h5xx_hal_msp.c:62:6:HAL_MspInit 4 static
../Core/Src/stm32h5xx_hal_msp.c:82:6:HAL_ADC_MspInit 232 static
../Core/Src/stm32h5xx_hal_msp.c:116:6:HAL_ADC_MspDeInit 16 static
../Core/Src/stm32h5xx_hal_msp.c:138:6:HAL_DAC_MspInit 48 static
../Core/Src/stm32h5xx_hal_msp.c:172:6:HAL_DAC_MspDeInit 16 static
../Core/Src/stm32h5xx_hal_msp.c:200:6:HAL_FDCAN_MspInit 256 static
../Core/Src/stm32h5xx_hal_msp.c:248:6:HAL_FDCAN_MspDeInit 16 static
../Core/Src/stm32h5xx_hal_msp.c:277:6:HAL_UART_MspInit 256 static
../Core/Src/stm32h5xx_hal_msp.c:325:6:HAL_UART_MspDeInit 16 static

9
hpsg5-controller-stm32h5/Debug/Core/Src/stm32h5xx_it.cyclo Normal file
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@@ -0,0 +1,9 @@
../Core/Src/stm32h5xx_it.c:69:6:NMI_Handler 1
../Core/Src/stm32h5xx_it.c:84:6:HardFault_Handler 1
../Core/Src/stm32h5xx_it.c:99:6:MemManage_Handler 1
../Core/Src/stm32h5xx_it.c:114:6:BusFault_Handler 1
../Core/Src/stm32h5xx_it.c:129:6:UsageFault_Handler 1
../Core/Src/stm32h5xx_it.c:144:6:SVC_Handler 1
../Core/Src/stm32h5xx_it.c:157:6:DebugMon_Handler 1
../Core/Src/stm32h5xx_it.c:170:6:PendSV_Handler 1
../Core/Src/stm32h5xx_it.c:183:6:SysTick_Handler 1

70
hpsg5-controller-stm32h5/Debug/Core/Src/stm32h5xx_it.d Normal file
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@@ -0,0 +1,70 @@
Core/Src/stm32h5xx_it.o: ../Core/Src/stm32h5xx_it.c ../Core/Inc/main.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal.h \
../Core/Inc/stm32h5xx_hal_conf.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rcc.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_def.h \
../Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h5xx.h \
../Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h533xx.h \
../Drivers/CMSIS/Include/core_cm33.h \
../Drivers/CMSIS/Include/cmsis_version.h \
../Drivers/CMSIS/Include/cmsis_compiler.h \
../Drivers/CMSIS/Include/cmsis_gcc.h \
../Drivers/CMSIS/Include/mpu_armv8.h \
../Drivers/CMSIS/Device/ST/STM32H5xx/Include/system_stm32h5xx.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rcc_ex.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_gpio.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_gpio_ex.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_icache.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_dma.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_dma_ex.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_cortex.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_adc.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_adc.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_adc_ex.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_dac.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_dac_ex.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_flash.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_flash_ex.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pwr.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pwr_ex.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_uart.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_uart_ex.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_exti.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_fdcan.h \
../Core/Inc/stm32h5xx_it.h
../Core/Inc/main.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal.h:
../Core/Inc/stm32h5xx_hal_conf.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rcc.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_def.h:
../Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h5xx.h:
../Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h533xx.h:
../Drivers/CMSIS/Include/core_cm33.h:
../Drivers/CMSIS/Include/cmsis_version.h:
../Drivers/CMSIS/Include/cmsis_compiler.h:
../Drivers/CMSIS/Include/cmsis_gcc.h:
../Drivers/CMSIS/Include/mpu_armv8.h:
../Drivers/CMSIS/Device/ST/STM32H5xx/Include/system_stm32h5xx.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rcc_ex.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_gpio.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_gpio_ex.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_icache.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_dma.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_dma_ex.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_cortex.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_adc.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_adc.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_adc_ex.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_dac.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_dac_ex.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_flash.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_flash_ex.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pwr.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pwr_ex.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_uart.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_uart_ex.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_exti.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_fdcan.h:
../Core/Inc/stm32h5xx_it.h:

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9
hpsg5-controller-stm32h5/Debug/Core/Src/stm32h5xx_it.su Normal file
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@@ -0,0 +1,9 @@
../Core/Src/stm32h5xx_it.c:69:6:NMI_Handler 4 static
../Core/Src/stm32h5xx_it.c:84:6:HardFault_Handler 4 static
../Core/Src/stm32h5xx_it.c:99:6:MemManage_Handler 4 static
../Core/Src/stm32h5xx_it.c:114:6:BusFault_Handler 4 static
../Core/Src/stm32h5xx_it.c:129:6:UsageFault_Handler 4 static
../Core/Src/stm32h5xx_it.c:144:6:SVC_Handler 4 static
../Core/Src/stm32h5xx_it.c:157:6:DebugMon_Handler 4 static
../Core/Src/stm32h5xx_it.c:170:6:PendSV_Handler 4 static
../Core/Src/stm32h5xx_it.c:183:6:SysTick_Handler 8 static

42
hpsg5-controller-stm32h5/Debug/Core/Src/subdir.mk Normal file
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@@ -0,0 +1,42 @@
################################################################################
# Automatically-generated file. Do not edit!
# Toolchain: GNU Tools for STM32 (14.3.rel1)
################################################################################
# Add inputs and outputs from these tool invocations to the build variables
C_SRCS += \
../Core/Src/main.c \
../Core/Src/stm32h5xx_hal_msp.c \
../Core/Src/stm32h5xx_it.c \
../Core/Src/syscalls.c \
../Core/Src/sysmem.c \
../Core/Src/system_stm32h5xx.c
OBJS += \
./Core/Src/main.o \
./Core/Src/stm32h5xx_hal_msp.o \
./Core/Src/stm32h5xx_it.o \
./Core/Src/syscalls.o \
./Core/Src/sysmem.o \
./Core/Src/system_stm32h5xx.o
C_DEPS += \
./Core/Src/main.d \
./Core/Src/stm32h5xx_hal_msp.d \
./Core/Src/stm32h5xx_it.d \
./Core/Src/syscalls.d \
./Core/Src/sysmem.d \
./Core/Src/system_stm32h5xx.d
# Each subdirectory must supply rules for building sources it contributes
Core/Src/%.o Core/Src/%.su Core/Src/%.cyclo: ../Core/Src/%.c Core/Src/subdir.mk
arm-none-eabi-gcc "$<" -mcpu=cortex-m33 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32H533xx -c -I../Core/Inc -I../Drivers/STM32H5xx_HAL_Driver/Inc -I../Drivers/STM32H5xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32H5xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mthumb -o "$@"
clean: clean-Core-2f-Src
clean-Core-2f-Src:
-$(RM) ./Core/Src/main.cyclo ./Core/Src/main.d ./Core/Src/main.o ./Core/Src/main.su ./Core/Src/stm32h5xx_hal_msp.cyclo ./Core/Src/stm32h5xx_hal_msp.d ./Core/Src/stm32h5xx_hal_msp.o ./Core/Src/stm32h5xx_hal_msp.su ./Core/Src/stm32h5xx_it.cyclo ./Core/Src/stm32h5xx_it.d ./Core/Src/stm32h5xx_it.o ./Core/Src/stm32h5xx_it.su ./Core/Src/syscalls.cyclo ./Core/Src/syscalls.d ./Core/Src/syscalls.o ./Core/Src/syscalls.su ./Core/Src/sysmem.cyclo ./Core/Src/sysmem.d ./Core/Src/sysmem.o ./Core/Src/sysmem.su ./Core/Src/system_stm32h5xx.cyclo ./Core/Src/system_stm32h5xx.d ./Core/Src/system_stm32h5xx.o ./Core/Src/system_stm32h5xx.su
.PHONY: clean-Core-2f-Src

18
hpsg5-controller-stm32h5/Debug/Core/Src/syscalls.cyclo Normal file
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@@ -0,0 +1,18 @@
../Core/Src/syscalls.c:44:6:initialise_monitor_handles 1
../Core/Src/syscalls.c:48:5:_getpid 1
../Core/Src/syscalls.c:53:5:_kill 1
../Core/Src/syscalls.c:61:6:_exit 1
../Core/Src/syscalls.c:67:27:_read 2
../Core/Src/syscalls.c:80:27:_write 2
../Core/Src/syscalls.c:92:5:_close 1
../Core/Src/syscalls.c:99:5:_fstat 1
../Core/Src/syscalls.c:106:5:_isatty 1
../Core/Src/syscalls.c:112:5:_lseek 1
../Core/Src/syscalls.c:120:5:_open 1
../Core/Src/syscalls.c:128:5:_wait 1
../Core/Src/syscalls.c:135:5:_unlink 1
../Core/Src/syscalls.c:142:5:_times 1
../Core/Src/syscalls.c:148:5:_stat 1
../Core/Src/syscalls.c:155:5:_link 1
../Core/Src/syscalls.c:163:5:_fork 1
../Core/Src/syscalls.c:169:5:_execve 1

1
hpsg5-controller-stm32h5/Debug/Core/Src/syscalls.d Normal file
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@@ -0,0 +1 @@
Core/Src/syscalls.o: ../Core/Src/syscalls.c

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18
hpsg5-controller-stm32h5/Debug/Core/Src/syscalls.su Normal file
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@@ -0,0 +1,18 @@
../Core/Src/syscalls.c:44:6:initialise_monitor_handles 4 static
../Core/Src/syscalls.c:48:5:_getpid 4 static
../Core/Src/syscalls.c:53:5:_kill 16 static
../Core/Src/syscalls.c:61:6:_exit 16 static
../Core/Src/syscalls.c:67:27:_read 32 static
../Core/Src/syscalls.c:80:27:_write 32 static
../Core/Src/syscalls.c:92:5:_close 16 static
../Core/Src/syscalls.c:99:5:_fstat 16 static
../Core/Src/syscalls.c:106:5:_isatty 16 static
../Core/Src/syscalls.c:112:5:_lseek 24 static
../Core/Src/syscalls.c:120:5:_open 12 static
../Core/Src/syscalls.c:128:5:_wait 16 static
../Core/Src/syscalls.c:135:5:_unlink 16 static
../Core/Src/syscalls.c:142:5:_times 16 static
../Core/Src/syscalls.c:148:5:_stat 16 static
../Core/Src/syscalls.c:155:5:_link 16 static
../Core/Src/syscalls.c:163:5:_fork 8 static
../Core/Src/syscalls.c:169:5:_execve 24 static

1
hpsg5-controller-stm32h5/Debug/Core/Src/sysmem.cyclo Normal file
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@@ -0,0 +1 @@
../Core/Src/sysmem.c:53:7:_sbrk 3

1
hpsg5-controller-stm32h5/Debug/Core/Src/sysmem.d Normal file
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@@ -0,0 +1 @@
Core/Src/sysmem.o: ../Core/Src/sysmem.c

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1
hpsg5-controller-stm32h5/Debug/Core/Src/sysmem.su Normal file
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@@ -0,0 +1 @@
../Core/Src/sysmem.c:53:7:_sbrk 32 static

2
hpsg5-controller-stm32h5/Debug/Core/Src/system_stm32h5xx.cyclo Normal file
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@@ -0,0 +1,2 @@
../Core/Src/system_stm32h5xx.c:201:6:SystemInit 4
../Core/Src/system_stm32h5xx.c:323:6:SystemCoreClockUpdate 9

67
hpsg5-controller-stm32h5/Debug/Core/Src/system_stm32h5xx.d Normal file
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Core/Src/system_stm32h5xx.o: ../Core/Src/system_stm32h5xx.c \
../Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h5xx.h \
../Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h533xx.h \
../Drivers/CMSIS/Include/core_cm33.h \
../Drivers/CMSIS/Include/cmsis_version.h \
../Drivers/CMSIS/Include/cmsis_compiler.h \
../Drivers/CMSIS/Include/cmsis_gcc.h \
../Drivers/CMSIS/Include/mpu_armv8.h \
../Drivers/CMSIS/Device/ST/STM32H5xx/Include/system_stm32h5xx.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal.h \
../Core/Inc/stm32h5xx_hal_conf.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rcc.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_def.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rcc_ex.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_gpio.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_gpio_ex.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_icache.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_dma.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_dma_ex.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_cortex.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_adc.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_adc.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_adc_ex.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_dac.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_dac_ex.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_flash.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_flash_ex.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pwr.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pwr_ex.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_uart.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_uart_ex.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_exti.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_fdcan.h
../Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h5xx.h:
../Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h533xx.h:
../Drivers/CMSIS/Include/core_cm33.h:
../Drivers/CMSIS/Include/cmsis_version.h:
../Drivers/CMSIS/Include/cmsis_compiler.h:
../Drivers/CMSIS/Include/cmsis_gcc.h:
../Drivers/CMSIS/Include/mpu_armv8.h:
../Drivers/CMSIS/Device/ST/STM32H5xx/Include/system_stm32h5xx.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal.h:
../Core/Inc/stm32h5xx_hal_conf.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rcc.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_def.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rcc_ex.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_gpio.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_gpio_ex.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_icache.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_dma.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_dma_ex.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_cortex.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_adc.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_adc.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_adc_ex.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_dac.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_dac_ex.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_flash.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_flash_ex.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pwr.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pwr_ex.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_uart.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_uart_ex.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_exti.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_fdcan.h:

BIN
hpsg5-controller-stm32h5/Debug/Core/Src/system_stm32h5xx.o Normal file
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2
hpsg5-controller-stm32h5/Debug/Core/Src/system_stm32h5xx.su Normal file
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@@ -0,0 +1,2 @@
../Core/Src/system_stm32h5xx.c:201:6:SystemInit 16 static
../Core/Src/system_stm32h5xx.c:323:6:SystemCoreClockUpdate 40 static

2
hpsg5-controller-stm32h5/Debug/Core/Startup/startup_stm32h533retx.d Normal file
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@@ -0,0 +1,2 @@
Core/Startup/startup_stm32h533retx.o: \
../Core/Startup/startup_stm32h533retx.s

BIN
hpsg5-controller-stm32h5/Debug/Core/Startup/startup_stm32h533retx.o Normal file
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27
hpsg5-controller-stm32h5/Debug/Core/Startup/subdir.mk Normal file
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@@ -0,0 +1,27 @@
################################################################################
# Automatically-generated file. Do not edit!
# Toolchain: GNU Tools for STM32 (14.3.rel1)
################################################################################
# Add inputs and outputs from these tool invocations to the build variables
S_SRCS += \
../Core/Startup/startup_stm32h533retx.s
OBJS += \
./Core/Startup/startup_stm32h533retx.o
S_DEPS += \
./Core/Startup/startup_stm32h533retx.d
# Each subdirectory must supply rules for building sources it contributes
Core/Startup/%.o: ../Core/Startup/%.s Core/Startup/subdir.mk
arm-none-eabi-gcc -mcpu=cortex-m33 -g3 -DDEBUG -c -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mthumb -o "$@" "$<"
clean: clean-Core-2f-Startup
clean-Core-2f-Startup:
-$(RM) ./Core/Startup/startup_stm32h533retx.d ./Core/Startup/startup_stm32h533retx.o
.PHONY: clean-Core-2f-Startup

60
hpsg5-controller-stm32h5/Debug/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.cyclo Normal file
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@@ -0,0 +1,60 @@
../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c:143:19:HAL_Init 2
../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c:177:19:HAL_DeInit 1
../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c:211:13:HAL_MspInit 1
../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c:222:13:HAL_MspDeInit 1
../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c:245:26:HAL_InitTick 8
../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c:335:13:HAL_IncTick 1
../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c:346:17:HAL_GetTick 1
../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c:355:10:HAL_GetTickPrio 1
../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c:364:19:HAL_SetTickFreq 3
../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c:397:21:HAL_GetTickFreq 1
../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c:413:13:HAL_Delay 3
../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c:439:13:HAL_SuspendTick 1
../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c:455:13:HAL_ResumeTick 1
../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c:465:10:HAL_GetHalVersion 1
../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c:474:10:HAL_GetREVID 1
../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c:483:10:HAL_GetDEVID 1
../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c:492:10:HAL_GetUIDw0 1
../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c:501:10:HAL_GetUIDw1 1
../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c:510:10:HAL_GetUIDw2 1
../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c:539:6:HAL_DBGMCU_EnableDBGStopMode 1
../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c:548:6:HAL_DBGMCU_DisableDBGStopMode 1
../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c:557:6:HAL_DBGMCU_EnableDBGStandbyMode 1
../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c:566:6:HAL_DBGMCU_DisableDBGStandbyMode 1
../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c:605:6:HAL_VREFBUF_VoltageScalingConfig 1
../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c:621:6:HAL_VREFBUF_HighImpedanceConfig 1
../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c:633:6:HAL_VREFBUF_TrimmingConfig 1
../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c:645:19:HAL_EnableVREFBUF 3
../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c:671:6:HAL_DisableVREFBUF 1
../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c:724:6:HAL_SBS_EnableVddIO1CompensationCell 1
../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c:735:6:HAL_SBS_DisableVddIO1CompensationCell 1
../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c:746:6:HAL_SBS_EnableVddIO2CompensationCell 1
../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c:757:6:HAL_SBS_DisableVddIO2CompensationCell 1
../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c:770:6:HAL_SBS_VDDCompensationCodeSelect 1
../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c:785:6:HAL_SBS_VDDIOCompensationCodeSelect 1
../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c:796:10:HAL_SBS_GetVddIO1CompensationCellReadyFlag 2
../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c:805:10:HAL_SBS_GetVddIO2CompensationCellReadyFlag 2
../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c:820:6:HAL_SBS_VDDCompensationCodeConfig 1
../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c:839:6:HAL_SBS_VDDIOCompensationCodeConfig 1
../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c:852:10:HAL_SBS_GetNMOSVddCompensationValue 1
../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c:861:10:HAL_SBS_GetPMOSVddCompensationValue 1
../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c:870:10:HAL_SBS_GetNMOSVddIO2CompensationValue 1
../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c:880:10:HAL_SBS_GetPMOSVddIO2CompensationValue 1
../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c:890:6:HAL_SBS_FLASH_DisableECCNMI 1
../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c:900:6:HAL_SBS_FLASH_EnableECCNMI 1
../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c:910:10:HAL_SBS_FLASH_ECCNMI_IsDisabled 2
../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c:938:6:HAL_SBS_IncrementHDPLValue 1
../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c:953:10:HAL_SBS_GetHDPLValue 1
../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c:988:6:HAL_SBS_EPOCHSelection 1
../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c:1003:10:HAL_SBS_GetEPOCHSelection 1
../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c:1020:6:HAL_SBS_SetOBKHDPL 1
../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c:1037:10:HAL_SBS_GetOBKHDPL 1
../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c:1071:6:HAL_SBS_OpenAccessPort 1
../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c:1081:6:HAL_SBS_OpenDebug 1
../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c:1094:19:HAL_SBS_ConfigDebugLevel 2
../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c:1116:10:HAL_SBS_GetDebugLevel 1
../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c:1127:6:HAL_SBS_LockDebugConfig 1
../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c:1141:6:HAL_SBS_ConfigDebugSecurity 1
../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c:1153:10:HAL_SBS_GetDebugSecurity 1
../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c:1277:6:HAL_SBS_Lock 1
../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c:1298:19:HAL_SBS_GetLock 2

68
hpsg5-controller-stm32h5/Debug/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.d Normal file
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@@ -0,0 +1,68 @@
Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.o: \
../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal.h \
../Core/Inc/stm32h5xx_hal_conf.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rcc.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_def.h \
../Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h5xx.h \
../Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h533xx.h \
../Drivers/CMSIS/Include/core_cm33.h \
../Drivers/CMSIS/Include/cmsis_version.h \
../Drivers/CMSIS/Include/cmsis_compiler.h \
../Drivers/CMSIS/Include/cmsis_gcc.h \
../Drivers/CMSIS/Include/mpu_armv8.h \
../Drivers/CMSIS/Device/ST/STM32H5xx/Include/system_stm32h5xx.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rcc_ex.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_gpio.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_gpio_ex.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_icache.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_dma.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_dma_ex.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_cortex.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_adc.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_adc.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_adc_ex.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_dac.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_dac_ex.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_flash.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_flash_ex.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pwr.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pwr_ex.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_uart.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_uart_ex.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_exti.h \
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_fdcan.h
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal.h:
../Core/Inc/stm32h5xx_hal_conf.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rcc.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_def.h:
../Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h5xx.h:
../Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h533xx.h:
../Drivers/CMSIS/Include/core_cm33.h:
../Drivers/CMSIS/Include/cmsis_version.h:
../Drivers/CMSIS/Include/cmsis_compiler.h:
../Drivers/CMSIS/Include/cmsis_gcc.h:
../Drivers/CMSIS/Include/mpu_armv8.h:
../Drivers/CMSIS/Device/ST/STM32H5xx/Include/system_stm32h5xx.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rcc_ex.h:
../Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_gpio.h:
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55
hpsg5-controller-stm32h5/Debug/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_adc_ex.cyclo Normal file
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37
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21
hpsg5-controller-stm32h5/Debug/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dac.cyclo Normal file
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68
hpsg5-controller-stm32h5/Debug/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dac.d Normal file
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18
hpsg5-controller-stm32h5/Debug/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dac_ex.cyclo Normal file
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68
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49
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16
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12
hpsg5-controller-stm32h5/Debug/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_gpio.cyclo Normal file
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@@ -0,0 +1,12 @@
../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_gpio.c:178:6:HAL_GPIO_Init 17
../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_gpio.c:310:6:HAL_GPIO_DeInit 4
../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_gpio.c:391:15:HAL_GPIO_ReadPin 2
../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_gpio.c:426:6:HAL_GPIO_WritePin 2
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../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_gpio.c:476:6:HAL_GPIO_TogglePin 1
../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_gpio.c:502:19:HAL_GPIO_LockPin 2
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68
hpsg5-controller-stm32h5/Debug/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_gpio.d Normal file
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Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_gpio.o: \
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hpsg5-controller-stm32h5/Debug/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_gpio.su Normal file
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../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_gpio.c:563:6:HAL_GPIO_DisableHighSPeedLowVoltage 16 static
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18
hpsg5-controller-stm32h5/Debug/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_icache.cyclo Normal file
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@@ -0,0 +1,18 @@
../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_icache.c:171:19:HAL_ICACHE_ConfigAssociativityMode 2
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68
hpsg5-controller-stm32h5/Debug/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_icache.d Normal file
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@@ -0,0 +1,68 @@
Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_icache.o: \
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